STR911FAW44X6T STMicroelectronics, STR911FAW44X6T Datasheet - Page 87

• Manufacturer Part Number: STR911FAW44X6T
• Description: MCU 16/32BIT FLASH 128-TQFP
• Manufacturer: STMicroelectronics
• Series: STR9r

Specifications of STR911FAW44X6T

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Processor Series: STR911x
• Core: ARM966E-S
• 3rd Party Development Tools: EWARM, EWARM-BL, MCBSTR9, MCBSTR9U, MCBSTR9UME, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: STR9-COMSTICK, STR910-EVAL, STR91X-SK/HIT, STR91X-SK/IAR, STR91X-SK/KEI, STR91X-SK/RAI, STR9-DK/RAIS, STR91X-DK/IAR, STX-PRO/RAIS, STR912-D/RAIS, STR79-RVDK/CPP, STR79-RVDKCPP/9, STR79-RVDK, STR79-RVDK/9, STR9-RVDK/BAS, STR79-RVDK/UPG
• For Use With: 497-5067 - BOARD EVAL FOR STR910 FAMILY497-5066 - KIT STARTER KEIL FOR STR910497-5065 - KIT STARTER IAR KICKSTART STR912497-5064 - KIT STARTER FOR STR910 FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

STR91xFAxxx
7.12.4
I
V
Table 45.
1. The maximum hold time of the START condition has only to be met if the interface does not stretch the low
2. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
3. C
2
DDQ
Symbol
C electrical characteristics
t
t
t
t
t
SU:STO
HD:STA
HD:DAT
SU:STA
SU:DAT
t
period of SCL signal
undefined region of the falling edge of SCL.
t
t
HIGH
LOW
BUF
C
t
b
t
R
F
b
= total capacitance of one bus line in pF
= 2.7 - 3.6 V, V
Bus free time between a STOP
and START condition
Hold time START condition.
After this period, the first clock
pulse is generated
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated
START condition
Data hold time
Data setup time
Rise time of both SDA and SCL
signals
Fall time of both SDA and SCL
signals
Setup time for STOP condition
Capacitive load for each bus
line
I
2
C electrical characteristics
Parameter
DD
= 1.65 - 2 V, T
(2)
(1)
Doc ID 13495 Rev 6
A
= -40 / 85 °C unless otherwise specified.
Min
250
4.0
4.7
4.0
4.7
4.0
4.7
Standard I
0
1000
Max
300
400
2
C
20+0.1C
20+0.1C
Electrical characteristics
Min
100
0.6
1.3
0.6
1.3
0.6
0.6
(3)
(3)
0
Fast I
b
b
2
C
Max
300
300
400
Unit
pF
87/102
µs
µs
µs
µs
µs
ns
ns
ns
ns
µs