F272-BAG-T STMicroelectronics, F272-BAG-T Datasheet
F272-BAG-T
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F272-BAG-T Summary of contents
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... Real time clock and 32 kHz on-chip oscillator ■ 111 general purpose I/O lines – Individually programmable as input, output or special function – Programmable threshold (hysteresis) ■ Idle, power down and stand-by modes ■ Single voltage supply: 5V ±10% Rev 2 ST10F272B ST10F272E LQFP144 ( 1.4mm) (Thin Quad Flat Package) 1/182 www.st.com 1 ...
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... Flash data register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Flash non volatile write protection I register . . . . . . . . . . . . . . . . . . . . . 38 Flash non volatile access protection register Flash non volatile access protection register 1 low . . . . . . . . . . . . . . . . 39 Flash non volatile access protection register 1 high . . . . . . . . . . . . . . . 40 ST10F272B/ST10F272E ...
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... ST10F272B/ST10F272E 5.5.6 5.5.7 5.5.8 5.5.9 5.6 Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.7 Write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6 Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1 Selection among user-code, standard or selective bootstrap . . . . . . . . . . 46 6.2 Standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.3 Alternate and selective boot mode (ABM and SBM 6.3.1 6.3.2 6.3.3 7 Central processing unit (CPU ...
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... Synchronous reset (warm reset 20.4 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 20.5 Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 20.6 Bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 20.7 Reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 20.8 Reset application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 20.9 Reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 21 Power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 21.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 4/182 Open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 ST10F272B/ST10F272E ...
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... ST10F272B/ST10F272E 21.2 Power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 21.2.1 21.2.2 21.3 Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 21.3.1 21.3.2 21.3.3 21.3.4 22 Programmable output clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 112 23 Register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 23.1 Special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 23.2 X-registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 23.3 Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 23.4 Identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 24 Electrical characteristics ...
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... CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 24.8.19 External bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 24.8.20 High-speed synchronous serial interface (SSC) timing . . . . . . . . . . . . 174 25 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 26 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 6/182 Phase Locked Loop (PLL 150 Voltage Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 PLL Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 ST10F272B/ST10F272E ...
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... Flash non volatile access protection register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 22. Flash non volatile access protection register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 23. XBus flash volatile temporary access unprotection register . . . . . . . . . . . . . . . . . . . . . . . 40 Table 24. Flash write operations Table 25. ST10F272 boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 26. Standard instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 27. MAC instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 28. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 29. ...
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... Table 79. CLKOUT and READY timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Table 80. External bus arbitration timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Table 81. SSC master mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Table 82. SSC slave mode timings 175 Table 83. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Table 84. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 8/182 = 5V ± ST10F272B/ST10F272E = –40 to +125° 154 ...
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... Anti-aliasing filter and conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Figure 43. Input / output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Figure 44. Float waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Figure 45. Generation mechanisms for the CPU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Figure 46. ST10F272 PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Figure 47. Crystal oscillator and resonator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Figure 48. 32kHz crystal oscillator connection diagram 155 List of figures 9/182 ...
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... External bus arbitration (releasing the bus 172 Figure 60. External bus arbitration (regaining the bus 173 Figure 61. SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Figure 62. SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Figure 63. PQFP144 mechanical data and package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Figure 64. LQFP144 mechanical data and package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 10/182 ST10F272B/ST10F272E ...
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... These two derivatives slightly differ on the available RAM size and Analog Channel Input number. These points will be highlighted in the corresponding chapters. For all information that is common to the 2 derivatives, the generic ST10F272 name will be used. The ST10F272 combines high CPU performance ( million instructions per second) with high peripheral functionality and enhanced I/O-capabilities ...
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... Port5 channels. External Memory bus is affected by limitations on maximum speed and maximum capacitance load: ST10F272 is not able to address an external memory at 64MHz with 0 wait states. XPERCON register bit mapping modified according to new peripherals implementation (not fully compatible with ST10F269) ...
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... ST10F272B/ST10F272E Figure 1. Logic symbol XTAL1 XTAL2 XTAL3 XTAL4 RSTIN RSTOUT V AREF V AGND ST10F272 NMI STBY READY ALE WRL Port 5 16-bit Introduction Port 0 16-bit Port 1 16-bit Port 2 16-bit Port 3 15-bit Port 4 8-bit Port 6 8-bit Port 7 8-bit Port 8 8-bit RPD 13/182 ...
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... P7.2 / POUT2 P7.3 / POUT3 P7.4 / CC28IO P7.5 / CC29IO P7.6 / CC30IO P7.7 / CC31IO P5.0 / AN0 P5.1 / AN1 P5.2 / AN2 P5.3 / AN3 P5.4 / AN4 P5.5 / AN5 P5.6 / AN6 P5.7 / AN7 P5.8 / AN8 P5.9 / AN9 *: AN16 to AN23 are only available for the ST10F272E 14/182 ...
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... ST10F272B/ST10F272E Table 1. Pin description Symbol Pin Type I ... ... 5 O P6 I/O 9-16 I/O I ... ... I/O 12 P8 I/O 14 I/O I/O 15 I/O I 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 6 outputs can be configured as push-pull or open drain drivers ...
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... P2.7 CC7IO CAPCOM: CC7 capture input/compare output P2.8 CC8IO CAPCOM: CC8 capture input/compare output EX0IN Fast external interrupt 0 input ... ... ... P2.15 CC15IO CAPCOM: CC15 capture input/compare output EX7IN Fast external interrupt 7 input T7IN CAPCOM2: timer T7 count input ST10F272B/ST10F272E Function ...
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... ST10F272B/ST10F272E Table 1. Pin description (continued) Symbol Pin Type 65-70, I/O 73-80, I P3 P3.6 - P3.13, P3. I 15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 3 outputs can be configured as push- pull or open drain drivers ...
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... Address latch enable output. In case of use of external addressing or of multiplexed mode, this signal is the latch command of the address lines. ST10F272B/ST10F272E Function ...
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... P0H.7 External access enable pin. A low level applied to this pin during and after Reset forces the ST10F272 to start the program from the external memory space. A high level forces ST10F272 to start in the internal memory space. This pin is also used (when Stand-by mode is ...
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... NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the ST10F272 to go into power down mode. If NMI is high and PWDCFG =’0’, when PWRDN is executed, the part will continue to run in normal mode ...
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... ST10F272B/ST10F272E Table 1. Pin description (continued) Symbol Pin Type RPD 84 - 17, 46, 72,82, 109, 126, 136 18,45, 55,71, V 83,94 110, 127, 139 Timing pin for the return from interruptible power down mode and synchronous / asynchronous reset selection. Digital supply voltage = + 5V during normal operation, idle and power down modes ...
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... Functional description 3 Functional description The architecture of the ST10F272 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F272. Figure 3. Block diagram XRAM1 ...
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... ST10F272B/ST10F272E 4 Memory organization The memory space of the ST10F272 is configured in a unified memory architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space of 16M Bytes. The entire memory space can be accessed Byte wise or Word wise. ...
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... As the XRAM appears like external memory, it cannot be used as system stack or as register banks. The XRAM is not provided for single bit storage and therefore is not bit addressable. ST10F272B XRAM: 8K+2K Bytes of XRAM. The XRAM1 (2K Bytes) address range is 00’E000h - 00’E7FFh if enabled. The XRAM2 (8K Bytes) address range is after reset 09’0000h - 09’1FFFh and is mirrored every 16KByte boundary ...
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... Bytes of external memory can be connected to the microcontroller. Visibility of XBUS peripherals In order to keep the ST10F272 compatible with the ST10F168 / ST10F269, the XBUS peripherals can be selected to be visible on the external address / data bus. Different bits for X-peripheral enabling in XPERCON register must be set. If these bits are cleared before the ...
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... Memory organization Figure 4. ST10F272 on-chip memory mapping (ROMEN=1 / XADRS = 800Bh - Reset value) Code Page Segment Segment FF FFFF 1023 11 FFFF 255 17 Ext. Memory 11 0000 10 FFFF 16 Ext. Memory 10 0000 0F FFFF XRAM2 XRAM2 15 XRAM2 XRAM2 0F 0000 0E FFFF XRAM2 XRAM2 14 XRAM2 XRAM2 0E 0000 XRAM2 0D FFFF ...
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... ST10F272B/ST10F272E 5 Internal Flash memory 5.1 Overview The on-chip Flash is composed by one matrix module, 256 KBytes wide. This module is on ST10 Internal bus called IFLASH Figure 5. Flash structure The programming operations of the flash are managed by an embedded Flash Program/Erase Controller (FPEC). The High Voltages needed for Program/Erase operations are internally generated ...
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... FFFF 32 KB 0x0002 0000 - 0x0002 FFFF 64 KB 0x0003 0000 - 0x0003 FFFF 64 KB 0x0004 0000 - 0x0004 FFFF 64 KB ST10F272B/ST10F272E operations)), and when accessed in Size ST10 Bus size ...
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... ST10F272B/ST10F272E When Bootstrap mode is entered: ● Test-Flash is seen and available for code fetches (address 00’0000h) ● User I-Flash is only available for read and write accesses ● Write accesses must be made with addresses starting in segment 1 from 01'0000h, whatever ROMS1 bit in SYSCON value ● ...
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... Flash Control Registers. Power supply drop If during a write operation the internal low voltage supply drops below a certain internal voltage threshold, any write operation running is suddenly interrupted and the module is reset to Read mode. At following Power-on, the interrupted Flash write operation must be repeated. 30/182 ST10F272B/ST10F272E ...
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... ST10F272B/ST10F272E 5.4 Registers description 5.4.1 Flash control register 0 low The Flash Control Register 0 Low (FCR0L) together with the Flash Control Register 0 High (FCR0H) is used to enable and to monitor all the write operations on the IFLASH. The user has no access in write mode to the Test-Flash (B0TF). Besides, Test-Flash block is seen by the user in Bootstrap Mode only ...
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... Flash Address to be programmed must be written in the FARH/L registers, while the Flash Data to be programmed must be written in the FDR0H/L registers before starting the execution by setting bit WMS. WPG bit is automatically reset at the end of the Word Program operation. 32/182 FCR reserved SPR ST10F272B/ST10F272E Reset value reserved Function 0000h 1 0 ...
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... ST10F272B/ST10F272E Table 8. Flash control register 0 high (continued) Bit Suspend This bit must be set to suspend the current Program (Word or Double Word) or Sector Erase operation in order to read data in one of the Sectors of the Bank under modification or to program data in another Bank. The Suspend operation resets the Flash Bank to normal read mode (automatically resetting bit BSY0) ...
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... Word Program (32-bit), Double Word Program (64-bit) and Set Protection. 34/182 FCR B0S RS B0S = 1 meaning FCR ST10F272B/ST10F272E Reset value reserved Function B0Fy = 1 meaning Erase Error in Sector y of Bank 0 Erase Suspended in Sector y of Bank 0 Don’t care Reset value Function 0000h ...
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... ST10F272B/ST10F272E 5.4.6 Flash data register 0 high FDR0H (0x08 000A DIN31 DIN30 DIN29 DIN28 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16 Table 13. Flash data register 0 high Bit Data Input 31:16 These bits must be written with the Data to program the Flash with the following ...
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... Bit Address 20:16 ADD(20:16) These bits must be written with the Address of the Flash location to program in the following operations: Word Program and Double Word Program. 36/182 FCR FCR reserved ST10F272B/ST10F272E Reset value Function Reset value ADD20 ADD19 ADD18 ADD17 ADD16 Function 0000h 1 0 ...
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... ST10F272B/ST10F272E 5.4.11 Flash error register Flash Error register, as well as all the other Flash registers, can be properly read only once LOCK bit of register FCR0L is low. Nevertheless, its content is updated when also BSY0 bit is reset as well; for this reason definitively meaningful reading FER register content only when LOCK bit and BSY0 bit are cleared ...
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... Flash non volatile write protection I register FNVWPIR (0x08 DFB0 Table 19. Flash non volatile write protection I register Bit Write Protection Bank 0 / Sectors 9-0 (IFLASH) W0P(9:0) These bits, if programmed at 0, disable any write access to the sectors of Bank 0 (IFLASH) 38/182 NVR reserved W0P7W0P6W0P5W0P4W0P3W0P2W0P1W0P0 RW ST10F272B/ST10F272E Reset value: FFFFh Function ...
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... ST10F272B/ST10F272E 5.5.3 Flash non volatile access protection register 0 FNVAPR0 (0x08 DFB8 Table 20. Flash non volatile access protection register 0 Bit Access Protection This bit, if programmed at 0, disables any access (read/write) to data mapped ACCP inside IFlash Module address space, unless the current instruction is fetched from IFlash ...
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... FNVAPR1L. The action to disable and enable again Access Protections in a permanent way can be executed a maximum of 16 times. To execute the above described operations, the Flash has to be temporary unprotected (See 40/182 NVR NVR reserved ST10F272B/ST10F272E Delivery value: FFFFh Function Reset value: 0000h Function Section 5.5.9: Temporary unprotection ...
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... ST10F272B/ST10F272E Trying to write into the access protected Flash from internal RAM or external memories will be unsuccessful. Trying to read into the access protected Flash from internal RAM or external memories will output a dummy data (software trap 0x009Bh). When the Flash module is protected in access, also the data access through PEC of a peripheral is forbidden ...
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... Add in FARH*/ /*Load Data in FDR0L*/ /*Load Data in FDR0H*/ /*Operation start*/ /*Set DWPG/ /*Load Add in FARL*/ /*Load Add in FARH*/ /*Load Data in FDR0L*/ /*Load Data in FDR0H*/ /*Load Data in FDR1L*/ /*Load Data in FDR1H*/ /*Operation start*/ /*Set SER in FCR0H*/ /*Set B0F1, B0F0*/ /*Operation start*/ ST10F272B/ST10F272E ...
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... ST10F272B/ST10F272E Suspend and resume Word Program, Double Word Program, and Sector Erase operations can be suspended in the following way: FCR0H |= 0x4000; Then the operation can be resumed in the following way: FCR0H |= 0x0800; FCR0H |= 0x8000; Before resuming a suspended Erase, FCR1H/FCR1L must be read to check if the Erase is already completed (FCR1H = FCR1L = 0x0000 if Erase is complete) ...
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... Add of register FNVAPR1L in FARH*/ = 0xFFFE; /*Load Data in FDR0L for clearing PDS0*/ /*Operation start*/ = 0x0001; /*Set TAUB in XFVTAUR0*/ /*Set SPR in FCR0H*/ = 0xDFBC; /*Load Add register FNVAPR1H in FARL*/ = 0x0008; /*Load Add register FNVAPR1H in FARH*/ = 0xFFFE; /*Load Data in FDR0H for clearing /*Operation start*/ /*Reset TAUB in XFVTAUR0*/ ST10F272B/ST10F272E ...
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... ST10F272B/ST10F272E 5.7 Write operation summary In general, each write operation is started through a sequence of 3 steps: 1. The first instruction is used to select the desired operation by setting its corresponding selection bit in the Flash Control Register 0. 2. The second step is the definition of the Address and Data for programming or the Sectors or Banks to erase ...
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... Standard bootstrap loader After entering the standard BSL mode and the respective initialization, the ST10F272 scans the RxD0 line and the CAN1_RxD line to receive either a valid dominant bit from CAN interface start condition from UART line. Start condition on UART RxD: ST10F272 starts standard bootstrap loader. This bootstrap loader is identical to other ST10 devices (example: ST10F269, ST10F168) ...
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... ST10F272B/ST10F272E 6.3 Alternate and selective boot mode (ABM and SBM) 6.3.1 Activation of the ABM and SBM Alternate boot is activated with the combination ‘01’ on Port0L[5..4] at the rising edge of RSTIN. 6.3.2 User mode signature integrity check The behavior of the Selective Boot Mode is based on the computing of a signature between the content of 2 memory locations and a comparison with a reference signature ...
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... SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most of the ST10F272’s instructions can be executed in one instruction cycle which requires 31.25ns at 64 MHz CPU clock. For example, shift and rotate instructions are processed in one instruction cycle independent of the number of bits to be shifted ...
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... ST10F272B/ST10F272E 7.1 Multiplier-accumulator unit (MAC) The MAC co-processor is a specialized co-processor added to the ST10 CPU Core in order to improve the performances of the ST10 Family in signal processing algorithms. The standard ST10 CPU has been modified to include new addressing capabilities which enable the CPU to supply the new co-processor with operands per instruction cycle. ...
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... Central processing unit (CPU) 7.2 Instruction set summary The Table 26 lists the instructions of the ST10F272. The detailed description of each instruction can be found in the “ST10 Family Programming Manual”. Table 26. Standard instruction set summary Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) ...
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... ST10F272B/ST10F272E Table 26. Standard instruction set summary (continued) Mnemonic J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP Description Jump relative if direct bit is (not) set ...
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... Central processing unit (CPU) 7.3 MAC co-processor specific instructions The Table 27 lists the MAC instructions of the ST10F272. The detailed description of each instruction can be found in the “ST10 Family Programming Manual”. Note that all MAC instructions are encoded on 4 Bytes. Table 27. MAC instruction set summary ...
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... ST10F272B/ST10F272E 8 External bus controller All of the external memory accesses are performed by the on-chip external bus controller. The EBC can be programmed to single chip mode when no external memory is required one of four different external memory access modes: ● 16- / 18- / 20- / 24-bit addresses and 16-bit data, demultiplexed ● ...
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... When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited to perform the transmission or the reception of blocks of data. The ST10F272 has 8 PEC channels, each of them offers such fast interrupt-driven data transfer capabilities. ...
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... ST10F272B/ST10F272E Table 28. Interrupt sources (continued) Source of Interrupt or PEC Service Request CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM Register 9 CAPCOM Register 10 CAPCOM Register 11 CAPCOM Register 12 CAPCOM Register 13 CAPCOM Register 14 CAPCOM Register 15 CAPCOM Register 16 CAPCOM Register 17 CAPCOM Register 18 CAPCOM Register 19 CAPCOM Register 20 CAPCOM Register 21 ...
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... XP2IE XP2INT XP3IR XP3IE XP3INT 2 C, PWM1 and RTC need some resources to implement interrupt Figure 9, the principle is explained through a simple XIRxSEL[15:8] Interrupt Enable bits XIRxSEL[7:0] Interrupt Flag bits ST10F272B/ST10F272E Vector Trap Location Number 00’0098h 26h 00’009Ch 27h 00’00A0h 28h 00’00A4h 29h 00’ ...
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... ST10F272B/ST10F272E available vector. If more than one source is enabled to issue the request, the service routine will have to take care to identify the real event to be serviced. This can easily be done by checking the flag bits (Byte Low of XIRxSEL register). Note that the flag bits can also ...
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... BTRAP 00’0028h MACTRP BTRAP 00’0028h PRTFLT BTRAP 00’0028h ILLOPA BTRAP 00’0028h ILLINA BTRAP 00’0028h ILLBUS BTRAP 00’0028h [002Ch - 003Ch] Any 0000h – 01FCh in steps of 4h ST10F272B/ST10F272E XP2INT XP3INT Trap Trap* Number Priority 00h III 00h III 00h III 02h II 04h II 06h ...
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... ST10F272B/ST10F272E 10 Capture / compare (CAPCOM) units The ST10F272 has two 16-channel CAPCOM units which support generation and control of timing sequences channels with a maximum resolution of 125ns at 64 MHz CPU clock. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events ...
Page 60
... ST10F272B/ST10F272E Function 100b 101b 110b 64 128 256 512 312.5 156.25 78.125 kHz kHz kHz 3.2µs 6.4µs 12.8µs 209.7ms 419.4ms 838.9ms ...
Page 61
... ST10F272B/ST10F272E 11 General purpose timer unit The GPT unit is a flexible multifunctional timer/counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized into two separate modules GPT1 and GPT2 ...
Page 62
... T2 2n n=3...10 Mode Reload Control Capture 2n n=3...10 T3 Mode Control Capture T4 Reload Mode Control 2n n=3...10 ST10F272B/ST10F272E 100b 101b 110b 3.2µs 6.4µs 12.8µs 209.7ms 419.4ms 838.9ms 100b 101b 110b 128 256 512 500 kHz 250 kHz 128 kHz 2.0µ ...
Page 63
... ST10F272B/ST10F272E 11.2 GPT2 The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) ...
Page 64
... Figure 11. Block diagram of GPT2 T5EUD CPU Clock T5IN CAPIN T6IN CPU Clock T6EUD 64/182 T5 2n n=2...9 GPT2 Timer T5 Mode Control Clear Capture GPT2 CAPREL T6 GPT2 Timer T6 Mode 2n n=2...9 Control ST10F272B/ST10F272E U/D Interrupt Request Interrupt Request Reload Interrupt Request Toggle FF T60TL T6OUT U/D to CAPCOM Timers ...
Page 65
... ST10F272B/ST10F272E 12 PWM modules Two pulse width modulation modules are available on ST10F272: standard PWM0 and XBUS PWM1. They can generate up to four PWM output signals each, using edge-aligned or centre-aligned PWM. In addition, the PWM modules can generate PWM burst signals and single shot outputs. The resolutions ...
Page 66
... I/O’s special features 13.2.1 Open drain mode Some of the I/O ports of ST10F272 support the open drain capability. This programmable feature may be used with an external pull-up resistor, in order to get an AND wired logical function. This feature is implemented for ports P2, P3, P4, P6, P7 and P8 (see respective sections), and is controlled through the respective Open Drain Control Registers ODPx ...
Page 67
... ST10F272B/ST10F272E 13.2.2 Input threshold control The standard inputs of the ST10F272 determine the status of input signals according to TTL levels. In order to accept and recognize noisy signals, CMOS input thresholds can be selected instead of the standard TTL thresholds for all the pins. These CMOS thresholds are defined above the TTL thresholds and feature a higher hysteresis to prevent the inputs from toggling while the respective input signal level is near the thresholds ...
Page 68
... All port lines that are not used for these alternate functions may be used as general purpose I/O lines. 68/182 ST10F272B/ST10F272E ...
Page 69
... The ST10F272E has 16+8 multiplexed input channels on Port 5 and Port 1. The selection between Port 5 and Port 1 is made via a bit in a XBus register. Refer to the User Manual for a detailed description. ...
Page 70
... CPU clock cycles. During this time, the busy flag ADBSY is set to indicate the operation. It compensates the capacitance mismatch, so the calibration procedure does not need any update during normal operation. No conversion can be performed during this time: the bit ADBSY shall be polled to verify when the calibration is over, and the module is able to start a convertion. 70/182 ST10F272B/ST10F272E ...
Page 71
... SSC1 (XBUS mapped). 15.1 Asynchronous / synchronous serial interfaces The asynchronous / synchronous serial interfaces (ASC0 and ASC1) provides serial communication between the ST10F272 and other microcontrollers, microprocessors or external peripherals. 15.2 ASCx in asynchronous mode In asynchronous mode 9-bit data transfer, parity generation and the number of stop bits can be selected ...
Page 72
... Baud rate crystal (providing a multiple of the ASC0 sampling frequency). 15.3 ASCx in synchronous mode In synchronous mode, data is transmitted or received synchronously to a shift clock which is generated by the ST10F272. Half-duplex communication Baud (at 40 MHz possible in this mode. Table 42. ASC synchronous baud rates by reload value and deviation errors (f S0BRS = ‘ ...
Page 73
... High speed synchronous serial interfaces The High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) provides flexible high- speed serial communication between the ST10F272 and other microcontrollers, microprocessors or external peripherals. The SSCx supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSCx itself (master mode received from an external master (slave mode) ...
Page 74
... Baud 489 Baud 74/182 list some possible Baud rates against the required reload values and Bit Time = 32 MHz (or CPU 3.26ms Bit Time = 32 MHz (or CPU = 48 MHz (or CPU 2.04ms ST10F272B/ST10F272E = 40 MHz) CPU Reload Value --- 0000h --- 0001h 150ns 0002h 200ns 0003h 400ns 0007h 1µs 0013h 10µ ...
Page 75
... ST10F272B/ST10F272E 16 I2C interface 2 The integrated I C Bus Module handles the transmission and reception of frames over the two-line SDA/SCL in accordance with the I operate in slave mode, in master mode or in multi-master mode. It can receive and transmit data using 7-bit or 10-bit addressing. Data can be transferred at speeds up to 400 Kbit/s ...
Page 76
... XMISCEN of XPERCON register and bit XPEN of SYSCON register. 17.2 CAN bus configurations Depending on application, CAN bus configuration may be one single bus with a single or multiple interfaces or a multiple bus with a single or multiple interfaces. The ST10F272 is able to support these two cases. 76/182 ST10F272B/ST10F272E 23. ...
Page 77
... Figure 13. Connection to single CAN bus via separate CAN transceivers CAN_H CAN_L The ST10F272 also supports single CAN Bus multiple (dual) interfaces using the open drain option of the CANx_TxD output as shown in Connection, only one transceiver is required. In this case the design of the application must take in account the wire length and the noise environment ...
Page 78
... CAN modules Multiple CAN bus The ST10F272 provides two CAN interfaces to support such kind of bus configuration as shown in Figure 15. Figure 15. Connection to two different CAN buses (e.g. for gateway application) CAN_H CAN_L Parallel Mode In addition to previous configurations, a parallel mode is supported. This is shown in Figure 16 ...
Page 79
... ST10F272B/ST10F272E 18 Real time clock The Real Time Clock is an independent timer, in which the clock is derived directly from the clock oscillator on XTAL1 (main oscillator) input or XTAL3 input (32 kHz low-power oscillator) so that it can be kept on running even in Idle or Power down mode (if enabled to). Registers access is implemented onto the XBUS. This module is designed with the following characteristics: ● ...
Page 80
... MHz and 64 MHz CPU = 40 MHz) CPU 2 (WDTIN = ‘0’) 12.8µs 3.277ms = 64 MHz) CPU 2 (WDTIN = ‘0’) 8µs 2.048ms ST10F272B/ST10F272E Prescaler for MHz CPU 128 (WDTIN = ‘1’) 819.2µs 209.7ms Prescaler for MHz CPU 128 (WDTIN = ‘1’) 512µ ...
Page 81
... ST10F272B/ST10F272E 20 System reset System reset initializes the MCU in a predefined state. There are six ways to activate a reset state. The system start-up configuration is different for each case as shown in Table 48. Reset event definition Reset Source Power-on reset Asynchronous Hardware reset Synchronous Long Hardware ...
Page 82
... Asynchronous reset An asynchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at low level. Then the ST10F272 is immediately (after the input filter delay) forced in reset default state. It pulls low RSTOUT pin, it cancels pending internal hold states if any, it aborts all internal/external bus cycles, it switches buses (data, address and control signals) and I/O pin drivers to high-impedance, it pulls high Port0 pins ...
Page 83
... ST10F272B/ST10F272E Warning: In next Figures 17 respectively with boot from internal or external memory, highlighting the reset phase extension introduced by the embedded FLASH module when selected. Note: Never power the device without keeping RSTIN pin grounded: the device could enter in unpredictable states, risking also permanent damages. ...
Page 84
... RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (Internal) FLARST RST 84/182 ST10F272B/ST10F272E ≤ 1.2 ms (for resonator oscillation + PLL stabilization) ≤ 10.2 ms (for crystal oscillation + PLL stabilization) ≥ (for on-chip VREG stabilization) ≤ 2 TCL ... ≥ ≤ 500 ns 3..4 TCL transparent not t. ...
Page 85
... ST10F272B/ST10F272E Figure 18. Asynchronous power-on RESET ( XTAL1 RPD RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] ALE RST Note TCL depending on clock source selection. Hardware reset The asynchronous reset must be used to recover from catastrophic situations of the application. It may be triggered by the hardware of the application. Internal hardware logic and application circuitry are described in Reset circuitry chapter and Figures 30, It occurs when RSTIN is low and RPD is detected (or becomes) low as well ...
Page 86
... Longer than 500ns to take into account of Input Filter on RSTIN pin 86/182 1) ≥ ≤ 500 ns ≥ ≤ 500 ns transparent not transparent not transparent transparent not transparent system start-up configuration ST10F272B/ST10F272E ≤ 2 TCL 3..4 TCL not t. not t. not t. not t. 7 TCL ≤ Latching point of Port0 for ...
Page 87
... FLASH is used, the restarting occurs after the embedded FLASH initialization routine is completed. The system configuration is latched from Port0: ALE, RD and WR/WRL pins are driven to their inactive level. The ST10F272 starts program execution from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine ...
Page 88
... FLASH initialization when EA=1 (internal memory selected). Then, the code execution restarts. The system configuration is latched from Port0, and ALE, RD and WR/WRL pins are driven to their inactive level. The ST10F272 starts program execution from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine ...
Page 89
... ST10F272B/ST10F272E Synchronous reset and RPD pin Whenever the RSTIN pin is pulled low (by external hardware consequence of a Bidirectional reset), the RPD internal weak pull-down is activated. The external capacitance (if any) on RPD pin is slowly discharged through the internal weak pull-down. If the voltage level on RPD pin reaches the input low threshold (around 2.5V), the reset event becomes immediately asynchronous ...
Page 90
... TCL 8 TCL µ 200 A Discharge ST10F272B/ST10F272E ≤ 2 TCL not t. not t. 7 TCL ≤ this time RSTF is sampled HIGH or LOW SHORT or LONG reset 2) V > 2.5V Asynchronous Reset not entered RPD ...
Page 91
... ST10F272B/ST10F272E Figure 22. Synchronous short / long hardware RESET ( RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] ALE RST RSTOUT RPD Notes: 1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation) the asynchronous reset is then immediately entered ...
Page 92
... TCL ≥ ≥ ≤ 500 ns ≤ 500 ns not transparent not t. transparent not transparent 1024+8 TCL µ 200 A Discharge ST10F272B/ST10F272E ≥ ≤ 2 TCL ≤ 500 ns 3..4 TCL transparent not t. not t. not t. 7 TCL ≤ this time RSTF is sampled LOW definitely LONG reset ...
Page 93
... ST10F272B/ST10F272E Figure 24. Synchronous long hardware RESET ( TCL RSTIN ≥ ≤ 500 ns RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] ALE RST RSTOUT RPD Notes during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered. ...
Page 94
... IBUS-CS (Internal) FLARST RST RSTOUT 94/182 25 and 26 for unidirectional SW reset timing, and to Figures 27, 25 and 26 for unidirectional SW reset timing, and to Figures 27, not transparent transparent not transparent not transparent 1024 TCL ST10F272B/ST10F272E 28 28 ≤ 2 TCL not t. not t. 7 TCL ≤ and and ...
Page 95
... ST10F272B/ST10F272E Figure 26 WDT unidirectional RESET ( RSTIN P0[15:13] P0[12:8] P0[7:2] P0[1:0] ALE RST RSTOUT 20.6 Bidirectional reset As shown in the previous sections, the RSTOUT pin is driven active (low level) at the beginning of any reset sequence (synchronous/asynchronous hardware, software and watchdog timer resets). RSTOUT pin stays active low beyond the end of the initialization routine, until the protected EINIT instruction (End of Initialization) is completed ...
Page 96
... FLASH itself extend the internal reset duration well beyond the filter delay. Next Figures 27, Bidirectional reset events: In particular reset. 96/182 28 and 29 summarize the timing for Software and Watchdog Timer Figure 29 ST10F272B/ST10F272E shows the degeneration into Hardware ...
Page 97
... ST10F272B/ST10F272E Figure 27 WDT bidirectional RESET (EA=1) RSTIN RSTF (After Filter) P0[15:13] P0[12:8] P0[7:2] P0[1:0] IBUS-CS (Internal) FLARST RST RSTOUT ≥ ≥ ≤ 500 ns ≤ 500 ns not transparent transparent not transparent not transparent ≤ 1024 TCL System reset not t. not t. ≤ 2 TCL ...
Page 98
... Figure 28 WDT bidirectional RESET ( RSTIN ≥ ≤ 500 ns RSTF (After Filter) P0[15:13] P0[12:8] P0[7:2] P0[1:0] ALE RST RSTOUT 98/182 ST10F272B/ST10F272E ≥ ≤ 500 ns not transparent not t. transparent not transparent not t. not transparent 1024 TCL At this time RSTF is sampled HIGH WDT Reset is flagged in WDTCON 8 TCL ...
Page 99
... If bit PWDCFG of SYSCON register is set, an internal pull-up resistor is activated at the end of the reset sequence. This pull-up will charge any capacitor connected on RPD pin. The simplest way to reset the ST10F272 is to insert a capacitor C1 between RSTIN pin and V , and a capacitor between RPD pin and V ...
Page 100
... Figure 30. Minimum external reset circuitry The minimum reset circuit of the ST10F272 itself during software or watchdog triggered resets, because of the capacitor C1 that will keep the voltage on RSTIN pin above V sequence, and thus will trigger an asynchronous reset sequence. Figure 31 shows an example of a reset circuit. In this example, R1-C1 external circuit is only used to generate power-up or manual reset, and R0-C0 circuit on RPD is used for power-up reset and to exit from Power Down mode ...
Page 101
... ST10F272B/ST10F272E Figure 31. System reset circuit ST10F272 Figure 32. Internal (simplified) reset circuitry Internal Reset Signal External Hardware RSTIN o.d. R0 Open Drain Inverter RPD + C0 EINIT Instruction Clr Q Set Reset State Machine Clock SRST instruction Trigger watchdog overflow Clr Reset Sequence (512 CPU Clock Cycles) ...
Page 102
... Next two timing diagrams bidirectional internal reset events (Software and Watchdog) including in particular the external capacitances charge and discharge transients (refer also to external circuit scheme). Figure 33. Example of software or watchdog bidirectional reset ( 102/182 (Figure 33 and Figure 34) provides additional examples of ST10F272B/ST10F272E Figure 31 for the ...
Page 103
... ST10F272B/ST10F272E Figure 34. Example of software or watchdog bidirectional reset ( System reset 103/182 ...
Page 104
... Activated by internal logic for 1024 TCL 1032 + 12 TCL + max(4 TCL, 500ns) 1032 + 12 TCL + max(4 TCL, 500ns) 1032 + 12 TCL + max(4 TCL, 500ns) Activated by internal logic only for 1024 TCL 1032 + 12 TCL + max(4 TCL, 500ns) Activated by internal logic only for 1024 TCL ST10F272B/ST10F272E WDTCON Flags - ...
Page 105
... ST10F272B/ST10F272E Table 49. Reset event (continued) Event Synch Synch. (2) Software Reset Synch Synch Synch Synch. (2) Watchdog Reset Synch Synch can degenerate into a Long Hardware Reset and consequently differently flagged (see 2. When Bidirectional is active (and with RPD=0), it can be followed by a Short Hardware Reset and consequently differently flagged (see Section 20 ...
Page 106
... H.1 H.0 L.7 SALSEL CSSEL WRC BUSTYP CSSEL WRC SALSEL Port 4 Port 6 Logic Logic P0L.7 SYSCON BYTDIS WRCFG ST10F272B/ST10F272E L.6 L.5 L.4 L.3 L.2 L.1 L.0 BSL Res. ADP EMU Bootstrap Loader Internal Control Logic VSTBY BUSCON0 BUS ALE BTYP ACT0 ...
Page 107
... Power reduction modes Three different power reduction modes with different levels of power reduction have been implemented in the ST10F272. In Idle mode only CPU is stopped, while peripheral still operate. In Power Down mode both CPU and peripherals are stopped. In Stand-by mode the main power supply (V ...
Page 108
... A dedicated embedded low-power voltage regulator is implemented to generate the internal low voltage supply (about 1.65V in Stand-by mode) to bias all those circuits that shall remain active: the portion of XRAM (16Kbytes for ST10F272E), the RTC counters and 32 kHz on- chip oscillator amplifier. 108/182 ...
Page 109
... V 18SB from ST10F272 Core (active low signal) is low enough to be recognized as a logic “0” by the RAM interface (due to V for the RAM and an unwanted data corruption could occur. For this reason, an extra interface, powered by the switched supply, is used to prevent the RAM from this kind of potential corruption mechanism ...
Page 110
... During power-off phase important that the external hardware maintains a stable ground level on RSTIN pin, without any glitch, in order to avoid spurious exiting from reset status with unstable power supply. STBY ST10F272B/ST10F272E pin external voltage). becomes higher than about 1.0V, there 18 ), the Real Time Clock ...
Page 111
... ST10F272B/ST10F272E 21.3.4 Power reduction modes summary In the following Table 51: Power reduction modes Power reduction modes is reported. Table 51. Power reduction modes summary Mode Idle Power Down Stand- off off off off on on off off on on off off off on off off off on off ...
Page 112
... SYSCON possible to program the clock prescaling factor: in this way on P3.15 a prescaled value of the CPU clock can be output. When CLKOUT function is not enabled (bit CLKEN of register SYSCON cleared), P3.15 does not output any clock signal, even though XCLKOUTDIV register is programmed. 112/182 ST10F272B/ST10F272E ...
Page 113
... This section summarizes all registers implemented in the ST10F272, ordered by name. 23.1 Special function registers The following table lists all SFRs which are implemented in the ST10F272 in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “ ...
Page 114
... CAPCOM register 17 interrupt control register 32h CAPCOM register 18 B2h CAPCOM register 18 interrupt control register 33h CAPCOM register 19 B3h CAPCOM register 19 interrupt control register 34h CAPCOM register 20 B4h CAPCOM register 20 interrupt control register ST10F272B/ST10F272E Reset value 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h ...
Page 115
... ST10F272B/ST10F272E Table 52. List of special function registers (continued) Physical Name address CC21 FE6Ah CC21IC b F16Ah E CC22 FE6Ch CC22IC b F16Ch E CC23 FE6Eh CC23IC b F16Eh E CC24 FE70h CC24IC b F170h E CC25 FE72h CC25IC b F172h E CC26 FE74h CC26IC b F174h E CC27 FE76h CC27IC b F176h E CC28 FE78h CC28IC ...
Page 116
... MAC unit repeat word EFh MAC unit status word E1h Port 2 open drain control register E3h Port 3 open drain control register E5h Port 4 open drain control register E7h Port 6 open drain control register ST10F272B/ST10F272E Reset value - - 00h - - 00h - - 00h 0000h 0000h - - 00h - - 00h - - 00h ...
Page 117
... ST10F272B/ST10F272E Table 52. List of special function registers (continued) Physical Name address ODP7 b F1D2h E ODP8 b F1D6h E ONES b FF1Eh P0L b FF00h P0H b FF02h P1L b FF04h P1H b FF06h P2 b FFC0h P3 b FFC4h P4 b FFC8h P5 b FFA2h P6 b FFCCh P7 b FFD0h P8 b FFD4h P5DIDIS b FFA4h PECC0 ...
Page 118
... CPU stack underflow pointer register 89h CPU system configuration register 28h CAPCOM timer 0 register A8h CAPCOM timer 0 and timer 1 control register CEh CAPCOM timer 0 interrupt control register 2Ah CAPCOM timer 0 reload register ST10F272B/ST10F272E Reset value 0000h 0000h 0000h 0000h 0000h - - 00h 0000h 0000h ...
Page 119
... ST10F272B/ST10F272E Table 52. List of special function registers (continued) Physical Name address T1 FE52h T1IC b FF9Eh T1REL FE56h T2 FE40h T2CON b FF40h T2IC b FF60h T3 FE42h T3CON b FF42h T3IC b FF62h T4 FE44h T4CON b FF44h T4IC b FF64h T5 FE46h T5CON b FF46h T5IC b FF66h T6 FE48h T6CON b FF48h T6IC b FF68h T7 F050h ...
Page 120
... XPnIR bits (of XPnIC register) of the unused X-Peripheral nodes. 23.2 X-registers The following table lists all X-Bus registers which are implemented in the ST10F272 ordered by their name. The FLASH control registers are listed in a separate section, in spite of they also are physically mapped on X-Bus memory space. ...
Page 121
... ST10F272B/ST10F272E Table 53. List of XBus registers (continued) Name CAN1IF2CR CAN1IF2DA1 CAN1IF2DA2 CAN1IF2DB1 CAN1IF2DB2 CAN1IF2M1 CAN1IF2M2 CAN1IF2MC CAN1IP1 CAN1IP2 CAN1IR CAN1MV1 CAN1MV2 CAN1ND1 CAN1ND2 CAN1SR CAN1TR CAN1TR1 CAN1TR2 CAN2BRPER CAN2BTR CAN2CR CAN2EC CAN2IF1A1 CAN2IF1A2 CAN2IF1CM CAN2IF1CR CAN2IF1DA1 CAN2IF1DA2 CAN2IF1DB1 CAN2IF1DB2 CAN2IF1M1 CAN2IF1M2 CAN2IF1MC ...
Page 122
... I2C status register 1 EA04h I2C status register 2 ED14h RTC alarm register high byte ED12h RTC alarm register low byte ED00H RTC control register ED0Ch RTC divider counter high byte ST10F272B/ST10F272E Reset value 0000h 0000h 0000h 0001h 0000h 0000h 0000h 0000h FFFFh ...
Page 123
... ST10F272B/ST10F272E Table 53. List of XBus registers (continued) Name RTCDL RTCH RTCL RTCPH RTCPL XCLKOUTDIV XEMU0 XEMU1 XEMU2 XEMU3 XIR0CLR XIR0SEL XIR0SET XIR1CLR XIR1SEL XIR1SET XIR2CLR XIR2SEL XIR2SET XIR3CLR XIR3SEL XIR3SET XMISC XP1DIDIS XPEREMU XPICON XPOLAR XPP0 XPP1 XPP2 XPP3 XPT0 XPT1 XPT2 ...
Page 124
... XSSC control register E804h XSSC clear control register (write only) E802h XSSC set control register (write only) E880h XSSC port control register E808h XSSC receive buffer E806h XSSC transmit buffer ST10F272B/ST10F272E Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h ...
Page 125
... Flash registers ordered by name The following table lists all Flash Control Registers which are implemented in the ST10F272 ordered by their name. These registers are physically mapped on the IBus, except for XFVTAUR0, which is mapped on XBus. Note that these registers are not bit-addressable. ...
Page 126
... Internal memory size MEMSIZE Internal memory size (MEMSIZE) (in Kbyte) 040h for 256 Kbytes (ST10F272) Internal memory type ‘0h’: ROM-Less ‘1h’: (M) ROM memory MEMTYP ‘2h’: (S) Standard Flash memory ‘3h’: (H) High performance Flash memory (ST10F272) ‘4h...Fh’: Reserved 126/182 ESFR ...
Page 127
... IDCHIP ● IDMEM ● IDPROG ESFR PROGVPP R voltage DD voltage when programming EPROM or FLASH devices is calculated using the = 20 x [PROGVDD] / 256 (volts) - 40h for ST10F272 (5V). DD voltage (no need of external V PP 0403h 110xh (x = silicon revision) F040h 0040h Reset Value: 0040h PROGVDD R Function ...
Page 128
... V respected. In particular power-on and power-off of V transient, in order to avoid undesired current injection through the on-chip protection diodes. 128/182 Parameter ) must not exceed the values defined by the SS AREF ST10F272B/ST10F272E Values Unit -0.5 to +6.5 V -0.5 to +6 ± 10 ...
Page 129
... ST10F272B/ST10F272E 24.2 Recommended operating conditions Table 60. Recommended operating conditions Symbol V Operating supply voltage DD V Operationg stand-by supply voltage STBY V Operating analog reference voltage AREF T Ambient temperature under bias A T Junction temperature under bias J 1. The value of the V voltage is specified in the range 4.5 - 5.5 Volt. Nevertheless acceptable to exceed the upper STBY limit ( ...
Page 130
... LQFP 144 24.4 Parameter interpretation The parameters listed in the following tables represent the characteristics of the ST10F272 and its demands on the system. Where the ST10F272 logic provides signals with their respective timing characteristics, the symbol “CC” for Controller Characteristics, is included in the “Symbol” column. Where the external system must provide signals with their respective timing characteristics to the ST10F272, the symbol “ ...
Page 131
... ST10F272B/ST10F272E 24.5 DC characteristics ± 10 Table 63. DC characteristics Parameter Input low voltage (TTL mode) (except RSTIN, EA, NMI, RPD, XTAL1, READY) Input low voltage (CMOS mode) (except RSTIN, EA, NMI, RPD, XTAL1, READY) Input low voltage RSTIN, EA, NMI, RPD Input low voltage XTAL1 (CMOS only) ...
Page 132
... I – P6H I –500 P6L 6) I – P0H 7) I –100 P0L CC – IO (9) I – CC1 (1) (10) I – CC2 I – ID ST10F272B/ST10F272E Unit Test Condition max – – – – OH1 – – 0.5 mA OH1 I = – OH2 = – 750 µA – OH2 = – 150 µA ...
Page 133
... ST10F272B/ST10F272E Table 63. DC characteristics (continued) Parameter (12) Power Down supply current (RTC off, Oscillators off, Main Voltage Regulator off) (12) Power Down supply current (RTC on, Main Oscillator on, Main Voltage Regulator off) (12) Power Down supply current (RTC on, 32kHz Oscillator on, Main Voltage Regulator off) (12) ...
Page 134
... RSTIN pin this implies I/O current is not considered. The device is IH IH1min CPU . IH1min Clock Input Alternate data input latch Test mode Flash sense amplifier and column decoder ST10F272B/ST10F272E is expressed in MHz). This dependency is is expressed in MHz). This dependency is P2.0 CC0IO Output buffer DD ...
Page 135
... ST10F272B/ST10F272E Figure 38. Supply current versus the operating frequency (RUN and IDLE modes) 150 100 [MHz] CPU Electrical characteristics CC1 CC2 135/182 ...
Page 136
... Word or Double Word Programming time could be longer than the average value. 3. Bank Erase is obtained through a multiple Sector Erase operation (setting bits related to all sectors of the Bank). As ST10F272 implements only one bank, the Bank Erase operation is equivalent to Module and Chip Erase operations. 4. Not 100% tested, guaranteed by Design Characterization. ...
Page 137
... ST10F272B/ST10F272E Table 65. Flash data retention characteristics Number of program / erase cycles (-40°C ≤ T ≤ 125° 100 1,000 10,000 100,000 1. Two 64Kbyte Flash Sectors may be typically used to emulate 16Kbyte of EEPROM. Therefore, in case of an emulation of a 16Kbyte EEPROM, 100,000 Flash Program / Erase cycles are equivalent to 800,000 EEPROM Program/Erase cycles. For an efficient use of the EEPROM Emulation please refer to dedicated Application Note document (AN2061 - “ ...
Page 138
... The time that the two different actions during conversion take (sampling, and converting) can be programmed within a certain range in the ST10F272 relative to the CPU clock. The absolute time that is consumed by the different conversion steps therefore is independent from the general speed of the controller ...
Page 139
... ST10F272B/ST10F272E Fast conversion can be achieved by programming the respective times to their absolute possible minimum. This is preferable for scanning high frequency signals. The internal resistance of analog source and analog supply must be sufficiently low, however. High internal resistance can be achieved by programming the respective times to a higher value, or the possible maximum ...
Page 140
... Data Sheet represents the maximum error with respect to the entire characteristic combination of the Offset, Gain and Integral Linearity errors. The different errors may compensate each other depending on the relative sign of the Offset and Gain errors. Refer to 140/182 Figure 39): Figure 39, see TUE. ST10F272B/ST10F272E Figure 39. (Figure 39, see ...
Page 141
... ST10F272B/ST10F272E Figure 39. A/D conversion characteristic 3FF 3FE 3FD 3FC 3FB 3FA Digital Out 007 (HEX) 006 005 004 003 002 001 000 1 Offset Error OFS 24.7.4 Analog reference pins The accuracy of the A/D converter depends on how accurate is its analog reference: a noise in the reference results in at least that much error in a conversion ...
Page 142
... L substantially a switched capacitance, with a frequency S equal to 4pF, a resistance of 1MΩ where f represents the conversion rate at the considered and the sum ⋅ ----------------------------------------------------------------------------- - ST10F272B/ST10F272E INTERNAL CIRCUIT SCHEME V DD Channel Sampling Selection and Figure 40), in combination the external circuit ...
Page 143
... ST10F272B/ST10F272E The formula above provides a constraints for external network design, in particular on resistive path. A second aspect involving the capacitance network shall be considered. Assuming the three capacitances equivalent circuit reported in Figure 40), when the sampling phase is started (A/D switch close), a charge sharing phenomena is installed. ...
Page 144
... Noise f (Anti-aliasing Filtering Condition ≤ (Nyquist Filter pole) Sampled Signal Spectrum ( ----------- = ------------------------------------------------------------ ST10F272B/ST10F272E ) T S ≤ (filter resistance). Being C F (at the end of the A2 . The following equation must be A1 already charged ⋅ ⋅ the filter is very high with longer than the sampling time ...
Page 145
... ST10F272B/ST10F272E From this formula, in the worst case (when V assuming to accept a maximum error of half a count (~2.44mV immediately evident a constraints the next section an example of how to design the external network is provided, assuming some reasonable values for the internal parameters and making hypothesis on the characteristics of the analog signal to be sampled. ...
Page 146
... V The other conditions to be verified is the time constants of the transients are really and significantly shorter than the sampling period duration T For complete set of parameters characterizing the ST10F272 A/D Converter equivalent circuit, refer to Section 24.7: A/D converter characteristics on page ...
Page 147
... It begins to float when a 100mV change from the loaded V 24.8.2 Definition of internal timing The internal operation of the ST10F272 is controlled by the internal CPU clock f edges of the CPU clock can trigger internal (for example pipeline) or external (for example bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “ ...
Page 148
... XTAL 5.3 to 8MHz XTAL 8MHz XTAL 6.4 to 8MHz XTAL 64MHz XTAL 6.4MHz XTAL 8MHz XTAL 4MHz XTAL ST10F272B/ST10F272E TCLTCL TCLTCL TCL TCL Notes 1) 3) Default configuration Direct Drive (oscillator bypassed CPU clock via prescaler /2, an external crystal or resonator XTAL ...
Page 149
... Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off. 24.8.6 Oscillator watchdog (OWD) An on-chip watchdog oscillator is implemented in the ST10F272. This feature is used for safety operation with external crystal oscillator (available only when using direct drive mode with or without prescaler, so the PLL is not used to generate the CPU clock multiplying the frequency of the external crystal oscillator) ...
Page 150
... Baud rates, etc.) the deviation caused by the PLL jitter is negligible. Refer to next 24.8.8 Voltage Controlled Oscillator The ST10F272 implements a PLL which combines different levels of frequency dividers with a Voltage Controlled Oscillator (VCO) working as frequency multiplier. In the following table, a detailed summary of the internal settings and VCO frequency is reported. Table 69. ...
Page 151
... ST10F272B/ST10F272E Table 69. Internal PLL divider mechanism (continued) P0.15-13 XTAL (P0H.7-5) Frequency 6.4MHz 12MHz 4MHz The PLL input frequency range is limited 3.5MHz, while the VCO oscillation range 128MHz. The CPU clock frequency range when PLL is used 64MHz. Example 1 ● 4MHz XTAL ● ...
Page 152
... PLL module inside the device. Anyhow, the contribution of the digital noise to the global jitter is widely taken into account in the curves provided in Figure 152/182 3 noise, the R.M.S. value of the accumulated jitter is proportional to N, 46. ST10F272B/ST10F272E 3 . Assuming a noiseless 2 noise, the R.M.S. value of the 2 noise for N smaller 3 ...
Page 153
... ST10F272B/ST10F272E Figure 46. ST10F272 PLL jitter ±5 ±4 ±3 ±2 ±1 T JIT 0 0 24.8.10 PLL lock / unlock During normal operation, if the PLL gets unlocked for any reason, an interrupt request to the CPU is generated, and the reference clock (oscillator) is automatically disconnected from the PLL input: in this way, the PLL goes into free-running mode, providing the system with a ...
Page 154
... Value min. typ. max. 1.4 2.6 4.2 – 1.5 – 0.8 – 6 – 1 ST10F272 Resonator Unit max. µs 300 µs 250 +500 ps 2000 kHz 4000 Unit mA/V – V – ...
Page 155
... –40 to +125° Parameter Conditions Start-up 1) Normal run 2) Peak to Peak 2) Sine wave middle 2) Stable V DD ST10F272 crystal C A Electrical characteristics C = 35pF A max. min. typ. 430 Ω 850 Ω – 120 Ω 250 Ω – ) and the package capacitance ...
Page 156
... XTAL Symbol min. max 15.625 – OSC – – – – IL2 ST10F272B/ST10F272E = 18pF C = 22pF C = 27pF 150 kΩ 120 kΩ ) and the package capacitance 0 Direct drive with PLL usage prescaler CPU XTAL CPU XTAL min. max. min. max. 83.3 250 83.3 3 – ...
Page 157
... ST10F272B/ST10F272E Figure 49. External clock drive XTAL1 Note: When Direct Drive is selected, an external clock source can be used to drive XTAL1. The maximum frequency of the external clock source depends on the duty cycle: when 64MHz is used, 50% duty cycle shall be granted (low phase = high phase = 7.8ns); when for instance 32MHz is used, a 25% duty cycle can be accepted (minimum phase, high or low, again equal to 7 ...
Page 158
... A – – – 16 – – – – F – 4 – – ST10F272B/ST10F272E Variable CPU Clock 1/2 TCL = 1 to 64MHz min. max. TCL – 8 – A TCL – – A TCL – 8 – A TCL – 8 – A – 8 – A – 6 – TCL + 6 2TCL – 9 – ...
Page 159
... ST10F272B/ST10F272E Table 77. Multiplexed bus timings (continued) Symbol Parameter Latched CS low to Valid Data Latched CS hold after RD ALE fall. edge to RdCS, WrCS (with RW delay) ALE fall. edge to RdCS, WrCS (no RW delay) Address float after RdCS WrCS (with RW delay)1 Address float after RdCS WrCS (no RW ...
Page 160
... Electrical characteristics Figure 50. External memory cycle: Multiplexed bus, with/without read/write delay, normal ALE ALE t 6 CSx A23-A16 (A15-A8) BHE Read cycle Address/data bus (P0) RD Write cycle Address/data bus (P0) WR WRL WRH 160/182 Address Address Address ST10F272B/ST10F272E Data in Address Data out ...
Page 161
... ST10F272B/ST10F272E Figure 51. External memory cycle: Multiplexed bus, with/without read/write delay, extended ALE t 5 ALE t 6 CSx t 6 A23-A16 (A15-A8) BHE Read cycle t 6 Address/Data Bus (P0) RD Write cycle Address/Data Bus (P0) WR WRL WRH Address t 7 Address Address Electrical characteristics Data Data out ...
Page 162
... Electrical characteristics Figure 52. External memory cycle: Multiplexed bus, with/without r/w delay, normal ALE, r/w CS CLKOUT ALE A23-A16 (A15-A8) BHE Read Cycle Address/Data Bus (P0) RdCSx Write Cycle Address/Data Bus (P0) WrCSx 162/182 Address Address Address ST10F272B/ST10F272E Address Data Data Out ...
Page 163
... ST10F272B/ST10F272E Figure 53. External memory cycle: Multiplexed bus, with/without r/w delay, extended ALE, r/w CS CLKOUT t ALE t 6 A23-A16 (A15-A8) BHE Read cycle t 6 Address/Data Bus (P0) RdCSx Write cycle Address/data bus (P0) WrCSx Address t 7 Address Address Electrical characteristics Data Data out 163/182 ...
Page 164
... C 0 – – 16 – – – F – – – F – – F ST10F272B/ST10F272E Variable CPU Clock 1/2 TCL = 1 to 64MHz min. max. TCL – 8 – A TCL – – A 2TCL – 12.5 + – TCL – – A 2TCL – 9 – C 3TCL – 9 – C – ...
Page 165
... ST10F272B/ST10F272E Table 78. Demultiplexed bus timings (continued) Symbol Parameter ALE falling edge to Latched Latched CS low to Valid Data Latched CS hold after RD Address setup to RdCS WrCS 82 (with RW-delay) Address setup to RdCS WrCS 83 (no RW-delay) RdCS to Valid Data (with RW-delay) RdCS to Valid Data (no RW-delay) RdCS, WrCS Low Time ...
Page 166
... Electrical characteristics Figure 54. External memory cycle: Demultiplexed bus, with/without r/w delay, normal ALE CLKOUT ALE CSx A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RD Write cycle Data bus (P0) (D15-D8) D7-D0 WR WRL WRH 166/182 Address Data out ST10F272B/ST10F272E 41u t ( 28h t 18 Data ...
Page 167
... ST10F272B/ST10F272E Figure 55. Exteral memory cycle: Demultiplexed bus, with/without r/w delay, extended ALE CLKOUT ALE t CSx A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RD Write cycle Data bus (P0) (D15-D8) D7-D0 WR WRL WRH Address Electrical characteristics Data Data out 167/182 ...
Page 168
... Electrical characteristics Figure 56. External memory cycle: Demultipl. bus, with/without r/w delay, normal ALE, r/w CS CLKOUT ALE A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RdCSx Write cycle Data bus (P0) (D15-D8) D7-D0 WrCSx 168/182 Address Data out ST10F272B/ST10F272E Data ...
Page 169
... ST10F272B/ST10F272E Figure 57. External memory cycle: Demultiplexed bus, without r/w delay, extended ALE, r/w CS CLKOUT ALE A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RdCSx Write cycle Data bus (P0) (D15-D8) D7-D0 WrCSx Address Electrical characteristics Data Data out 169/182 ...
Page 170
... – 2 – 35 – 17 – 2 – and t A ST10F272B/ST10F272E Variable CPU Clock 1/2 TCL = 1 to 64MHz min. max. 2TCL 2TCL TCL – 3.5 – TCL – 2.5 – – 4 – 4 – – 2 – 2TCL + 10 – 17 – 2 – ...
Page 171
... ST10F272B/ST10F272E Figure 58. CLKOUT and READY CLKOUT ALE RD, WR Synchronous READY Asynchronous READY 1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS). 2. The leading edge of the respective command depends on RW-delay. 3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled LOW at this sampling point terminates the currently running bus cycle ...
Page 172
... Figure 59. External bus arbitration (releasing the bus) CLKOUT HOLD HLDA BREQ CSx (P6.x) Others 1. The ST10F272 will complete the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to become active. 3. The CS outputs will be resistive high (pull-up) after t 172/182 = 0V -40 to +125° ...
Page 173
... This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10F272 requesting the bus. 2. The next ST10F272 driven bus cycle may start here ...
Page 174
... CPU (<SSCBR> = 0002h) min. (2)) 150 63 63 – – – (3) – TCL x (<SSCBR> Where <SSCBR> represents the content of the SSC 300 ST10F272B/ST10F272E = 50pF L Variable Baudrate (<SSCBR> = 0001h - FFFFh) max. min. max. 150 8TCL 262144 TCL – – 12 – 300 – – ...
Page 175
... ST10F272B/ST10F272E Figure 61. SSC master timing 1) SCLK MTSR MRST 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b). ...
Page 176
... ST10F272B/ST10F272E Variable Baudrate (1) ) (<SSCBR> = 0001h - FFFFh) max. min. max. – 6 – 2TCL + 6 2) 313 t 316 315 Last out bit t t 317 ...
Page 177
... ST10F272B/ST10F272E 25 Package information To meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions, and product status are available at ECOPACK® trademark. Package information www.st.com. 177/182 ...
Page 178
... PQFP144 ST10F272B/ST10F272E OUTLINE AND MECHANICAL DATA PQFP144 0.10mm .004 Seating Plane C K ...
Page 179
... ST10F272B/ST10F272E Figure 64. LQFP144 mechanical data and package dimension DIM. MIN. TYP 0.05 A2 1.35 B 0.17 C 0.09 D 22.00 D1 20.00 D3 17. 22.00 E1 20.00 E3 17. Note 1: Exact shape of each corner is optional. mm inch MAX. MIN. TYP. MAX. 1.60 0.063 0.15 0.002 0.006 1.40 1.45 0.053 ...
Page 180
... Ordering information 26 Ordering information pecific Table 83. Order codes Part number F272-BAG-P F272-BAG-P-TR F272-BAG-T F272-BAG-T-TR 180/182 Package Packing Type Tray PQFP144 Tape and reel Tray LQFP144 Tape and reel ST10F272B/ST10F272E B/E Temperature CPU frequency range (°C) range (MHz) ° E -40 to +125 C ° ...
Page 181
... Name of all I2C registers corrected adding prefix “I2C” (Pages 201 - 202 and 204). Section 24.5: Note numbering and content in DC Characteristics table updated (Pages 222 to 225). Updated document to support both ST10F272B and ST10F272E 0.9 products. Updated Chapter 24: Electrical characteristics characteristics. ...
Page 182
... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 182/182 Please Read Carefully: © 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com ST10F272B/ST10F272E ...