F272-BAG-T STMicroelectronics, F272-BAG-T Datasheet - Page 134

• Manufacturer Part Number: F272-BAG-T
• Description: MCU 16BIT 256K FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of F272-BAG-T

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: ASC, CAN, I2C, SSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Electrical characteristics
10. The power supply current is a function of the operating frequency (f
11. The Idle mode supply current is a function of the operating frequency (f
12. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at V
134/182
illustrated in the
disconnected and all inputs at V
doing the following:
- Fetching code from all sectors of IFlash, accessing in read (few fetches) and write to XRAM
- Watchdog Timer is enabled and regularly serviced
- RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles
- Four channel of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling
- Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)
- ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5
- All interrupts generated by XPWM, RTC, Timers and ADC are not serviced
illustrated in the
and all inputs at V
– 0.1 V to V
Regulator is assumed off: in case it is not, additional 1mA shall be assumed.
DD
Figure 37. Port2 test mode structure
, V
Figure 38
Figure 37
AREF
IL
or V
= 0 V, all outputs (including pins configured as outputs) disconnected. Besides, the Main Voltage
IH
, RSTIN pin at V
below. This parameter is tested at V
below. These parameters are tested and at maximum CPU clock with all outputs disconnected
Fast external interrupt input
IL
or V
Flash sense amplifier
and column decoder
Alternate data input
IH
, RSTIN pin at V
IH1min
.
IH1min
DDmax
: this implies I/O current is not considered. The device is
CPU
Clock
Input
latch
and at maximum CPU clock frequency with all outputs
Test mode
CPU
is expressed in MHz). This dependency is
is expressed in MHz). This dependency is
Output
buffer
ST10F272B/ST10F272E
P2.0
CC0IO
DD