F272-BAG-T STMicroelectronics, F272-BAG-T Datasheet - Page 34

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F272-BAG-T

Manufacturer Part Number
F272-BAG-T
Description
MCU 16BIT 256K FLASH 144-TQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet

Specifications of F272-BAG-T

Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-TQFP, 144-VQFP
Processor Series
ST10F27x
Core
ST10
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
ASC, CAN, I2C, SSC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
111
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
F272-BAG-T
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
F272-BAG-T-TR
Manufacturer:
STMicroelectronics
Quantity:
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Part Number:
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Manufacturer:
ST
0
Internal Flash memory
5.4.4
5.4.5
34/182
Flash control register 1 high
The Flash Control Register 1 High (FCR1H), together with Flash Control Register 1 Low
(FCR1L), is used to select the Sectors to Erase, or during any write operation to monitor the
status of each Sector and Bank.
FCR1H (0x08 0006)
Table 10.
During any erase operation, this bit is automatically set and gives the status of the Bank 0.
The meaning of B0Fy bit for Sector y of Bank 0 is given by the next Table 4 Banks (BxS) and
Sectors (BxFy) Status bits meaning. These bits are automatically reset at the end of an
erase operation if no errors are detected.
Table 11.
Flash data register 0 low
The Flash Address Registers (FARH/L) and the Flash Data Registers (FDR1H/L-FDR0H/L)
are used during the program operations to store Flash Address in which to program and
Data to program.
FDR0L (0x08 0008)
Table 12.
DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0
B0S
DIN(15:0)
RW
ERR
15
15
1
0
0
Bit
Bit
RW
14
14
SUSP
1
0
-
RW
Banks (BxS) and sectors (BxFy) status bits meaning
13
13
Flash control register 1 high
Flash data register 0 low
Erase Error in Bank 0
Erase Suspended in Bank 0
Don’t care
reserved
Bank 0 Status (IFLASH)
During any erase operation, this bit is automatically modified and gives the status
of the Bank 0. The meaning of B0S bit is given in the next Table 4 Banks (BxS) and
Sectors (BxFy) Status bits meaning. This bit is automatically reset at the end of a
erase operation if no errors are detected.
Data Input 15:0
These bits must be written with the Data to program the Flash with the following
operations: Word Program (32-bit), Double Word Program (64-bit) and Set
Protection.
RW
12
12
RW
11
11
B0S = 1 meaning
RW
10
10
RW
9
9
FCR
FCR
B0S
RW
RS
8
8
RW
7
7
Function
Function
RW
Erase Error in Sector y of Bank 0
Erase Suspended in Sector y of Bank 0
Don’t care
6
6
RW
reserved
5
5
B0Fy = 1 meaning
RW
4
4
ST10F272B/ST10F272E
RW
3
3
Reset value:
Reset value:
RW
2
2
RW
1
1
FFFFh
0000h
RW
0
0

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