ST10F272M-4TR3 STMicroelectronics, ST10F272M-4TR3 Datasheet - Page 147

• Manufacturer Part Number: ST10F272M-4TR3
• Description: MCU 16BIT 256K FLASH 144-LQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F272M-4TR3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F272M
24.8.10
Note:
noise in the loop, with cutoff frequency equal to the bandwidth of the PLL. The saturation
value corresponds to what has been called self referred long term jitter of the PLL. In
Figure 46
CPU frequencies) is shown: The curves represent the very worst case, computed taking into
account all corners of temperature, power supply and process variations: The real jitter is
always measured well below the given worst case values.
Noise in supply and substrate
Digital supply noise adds deterministic components to the PLL output jitter, independent of
the multiplication factor. Its effects are strongly reduced thanks to the particular care used in
the physical implementation and integration of the PLL module inside the device.
Nonetheless, the contribution of the digital noise to the global jitter is widely taken into
account in the curves provided in
Figure 46. ST10F272M PLL jitter
PLL lock/unlock
During normal operation, if the PLL gets unlocked for any reason, an interrupt request to the
CPU is generated, and the reference clock (oscillator) is automatically disconnected from
the PLL input: in this way, the PLL goes into free-running mode, providing the system with a
backup clock signal (free running frequency f
failure occurrence without risking to go into an undefined configuration: The system is
provided with a clock allowing the execution of the PLL unlock interrupt routine in a safe
mode.
The path between reference clock and PLL input can be restored only by a hardware reset,
or by a bidirectional software or watchdog reset event that forces the RSTIN pin low.
The external RC circuit on RSTIN pin must be properly sized in order to extend the duration
of the low pulse to lock the PLL before the level at RSTIN pin is recognized high: A
bidirectional reset internally drives the RSTIN pin low for just 1024 TCL (definitly not
sufficient to lock the PLL starting from free-running mode).
the maximum jitter trend versus the number of clock periods N (for some typical
T
± 5
± 4
± 3
± 2
± 1
JIT
0
0
200
16MHz
400
Figure
24MHz
46.
N (CPU clock periods)
600
32MHz
free
). This feature allows recovery from a crystal
40MHz
800
1000
Electrical characteristics
1200
64MHz
1400
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