ST10F272M-4QR3 STMicroelectronics, ST10F272M-4QR3 Datasheet - Page 146

• Manufacturer Part Number: ST10F272M-4QR3
• Description: MCU 16BIT 256K FLASH 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F272M-4QR3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Electrical characteristics
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PLL jitter
The following terminology is defined below:
●
●
Jitter at the PLL output can be due to the following reasons:
●
●
Jitter in the input clock
PLL acts like a low pass filter for any jitter in the input clock. Input clock jitter with the
frequencies within the PLL loop bandwidth is passed to the PLL output and higher frequency
jitter (frequency > PLL bandwidth) is attenuated @20dB/decade.
Noise in the PLL loop
This contribution again can be caused by the following sources:
●
●
Device noise of the circuit in the PLL
The long term jitter is inversely proportional to the bandwidth of the PLL: the wider the loop
bandwidth is, the lower the jitter is due to noise in the loop. Moreover, the long term jitter is
practically independent of the multiplication factor.
The most noise sensitive circuit in the PLL circuit is definitively the VCO (voltage controlled
oscillator). There are two main sources of noise: thermal (random noise, frequency-
independent noise, thus, practically white noise) and flicker (low frequency noise, 1/f). For
the frequency characteristics of the VCO circuitry, the effect of the thermal noise results in a
1/f
noiseless PLL input and supposing that the VCO is dominated by its 1/f
value of the accumulated jitter is proportional to the square root of N, where N is the number
of clock periods within the considered time interval. On the contrary, assuming again a
noiseless PLL input and supposing that the VCO is dominated by its 1/f
value of the accumulated jitter is proportional to N, where N is the number of clock periods
within the considered time interval.
The jitter in the PLL loop can be modelized as dominated by the i1/f
than a certain value depending on the PLL output frequency and on the bandwidth
characteristics of loop. Above this first value, the jitter becomes dominated by the i1/f
component. Lastly, for N greater than a second value of N, a saturation effect is evident, so
the jitter does not grow anymore when considering a longer time interval (jitter stable
increasing the number of clock periods N). The PLL loop acts as a high pass filter for any
2
region in the output noise spectrum, while the flicker noise in a 1/f
Self referred single period jitter
Also called ‘period jitter’, it can be defined as the difference of the T
T
period of the PLL output clock.
Self referred long term jitter
Also called ‘N period jitter’, it can be defined as the difference of T
T
minimum time difference between N+1 clock rising edges. Here N should be kept
sufficiently large to have the long term jitter. For N = 1, this becomes the single period
jitter.
Jitter in the input clock
Noise in the PLL loop
Device noise of the circuit in the PLL
Noise in supply and substrate.
max
max
is maximum time period of the PLL output clock and T
is the maximum time difference between N+1 clock rising edges and T
min
2
is the minimum time
noise for N smaller
3
max
. Assuming a
max
2
3
noise, the RMS
noise, the RMS
and T
and T
ST10F272M
min
min
min
, where
, where
3
is the
noise