ST10F269-DPB STMicroelectronics, ST10F269-DPB Datasheet - Page 110

• Manufacturer Part Number: ST10F269-DPB
• Description: MCU 16BIT 256K FLASH 144PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F269-DPB

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-BFQFP
• Processor Series: ST10F26x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

ST10F269
The short hardware reset ends and the MCU restarts.To be processed as a short hardware reset, the
external RSTIN signal must last a maximum of 1038 TCL (4 TCL + 10 TCL + 1024 TCL). The system
configuration is latched from PORT0 after a duration of 8 TCL / 4 CPU clocks (6 TCL / 3 CPU clocks if PLL
is bypassed) and in case of external fetch, ALE, RD and R/W pins are driven to their inactive level.
Program execution starts from memory location 00'0000h in code segment 0. This starting location will
typically point to the general initialization routine.
summarized in Figure 57. Refer to Table 29 for PORT0 latched configuration.
Note
Figure 57 : Synchronous Warm Reset Sequence External Fetch (4 TCL < RSTIN pulse < 1038 TCL)
Note
18.3 - Software Reset
The reset sequence can be triggered at any time using the protected instruction SRST (software reset).
This instruction can be executed deliberately within a program, for example to leave bootstrap loader
mode, or upon a hardware trap that reveals a system failure.
Upon execution of the SRST instruction, the internal reset sequence (1024 TCL) is started. The
microcontroller behavior is the same as for a short hardware reset, except that only P0.12...P0.6 bits are
latched at the end of the reset sequence, while previously latched values of P0.5...P0.2 are cleared.
18.4 - Watchdog Timer Reset
When the watchdog timer is not disabled during the initialization or when it is not regularly serviced during
program execution it will overflow and it will trigger the reset sequence.
110/160
1) RSTIN assertion can be released there.
3) RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit BDRSTEN is cleared after
reset.
4) RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on
(f
5) If during the reset condition (RSTIN low), V
ST10 reset circuitry disables the bidirectional reset function and RSTIN pin is no more pulled low.
2) Maximum internal synchronisation is 6 CPU cycles (12 TCL).
CPU
- If the RSTIN pin level is sampled low, the reset sequence is extended until RSTIN level becomes
high leading to a long hardware reset (synchronous or asynchronous reset) because RSTIN
signal duration has lasted longer than 1040TCL.
- If the V
asynchronous reset.
CPU Clock
RSTIN
RPD
RSTOUT
ALE
RD
PORT0
Internal reset signal
= f
XTAL
/ 2 ), else it is 4 CPU clock cycles (8 TCL).
RPD
1)
voltage has droped below the RPD pin threshold, the reset is processed as an
4 TCL 10 TCL
min.
200 A Discharge
min.
2)
Internally pulled low
RPD
1024 TCL
voltage drops below the threshold voltage (typically 2.5V for 5V operation), the
If V
Reset is not entered.
RPD
Reset Configuration
> 2.5V Asynchronous
3)
Timings of synchronous reset sequence are
1
6 or 8 TCL
2
5)
3
4
4)
5
5 TCL
for system start-up configuration
Latching point of PORT0
6
7
8
9
1st Instr.