ST10F269-DPB STMicroelectronics, ST10F269-DPB Datasheet - Page 134

• Manufacturer Part Number: ST10F269-DPB
• Description: MCU 16BIT 256K FLASH 144PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F269-DPB

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-BFQFP
• Processor Series: ST10F26x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

ST10F269
21.3.1 - A/D Converter Characteristics
V
Table 32 : A/D Converter Characteristics
Notes: 1. V
134/160
V
V
I
C
t
t
DNL
INL
OFS
TUE
R
K
AREF
S
C
DD
AREF
AIN
AIN
ASRC
= 5V ± 10%, V
Symbol
X000h or X3FFh, respectively.
2. During the t
the analog source must allow the capacitance to reach its final voltage level within the t
time, changes of the analog input voltage have no effect on the conversion result. Values for the t
programming. Referring to the t
- t
- t
TCL is defined in Section 21.4.2 -, Section 21.4.4 -, and Section 21.4.5 - on page 138 :
3. The conversion time formula is:
- t
The t
the result of the conversion. Values for the t
- t
- t
4. This parameter is fixed by ADC control logic.
5. DNL, INL, TUE are tested at V
voltages within the defined voltage range.
‘LSB’ has a value of V
The specified TUE is guaranteed only if an overload condition (see I
pins and the absolute sum of input overload currents on all analog input pins does not exceed 10mA.
6. The coupling factor is measured on a channel while an overload condition occurs on the adjacent not selected channel with an
absolute overload current less than 10mA.
7. Partially tested, guaranteed by design characterization.
8.To remove noise and undesirable high frequency components from the analog input signal, a low-pass filter must be connected at
the ADC input. The cut-off frequency of this filter should avoid 2 opposite transitions during the t
- f
where t
S
S
C
C
C
cut-off
min = 2 t
max = 2 t
= 14 t
min = 14 t
max = 14 t
AIN
C
parameter includes the t
CC
CC
CC
CC
s
SR
SR
CC
CC
CC
CC
CC
SR
may exceed V
is the sampling time of the ST10 ADC and is not related to the Nyquist frequency determined by the t
CC
1 / 5 t
SC
+ t
SC
CC
S
CC
S
min = 2 t
sample time the input capacitance C
max = 2 x 8 t
s
Analog Reference voltage
Analog input voltage
Reference supply current
running mode
power-down mode
ADC input capacitance
Not sampling
Sampling
Sample time
Conversion time
Differential Nonlinearity
Integral Nonlinearity
Offset Error
Total unadjusted error
Internal resistance of analog source
Coupling Factor between inputs
SS
min + t
+ 4 TCL (= 14 t
max + t
to 1/10 t
= 0V
AREF
AGND
S
CC
S
min + 4 TCL = 14 x 24 x TCL + 48 TCL + 4 TCL = 388 TCL
,
s
max + 4 TCL = 14 x 96 TCL + 1536 TCL + 4 TCL = 2884 TCL
/ 1024.
min = 2 x 24 x TCL = 48 TCL
T
or V
A
CC
= -40 to +125°C, 4.0V V
C
S
max = 2 x 8 x 96 TCL = 1536 TCL
CC
AREF
Parameter
conversion time formula of Section 21.3.2 - on page 135 and to Table 33 on page 135:
sample time, the time for determining the digital result and the time to load the result register with
AREF
+ 2 t
up to the absolute maximum ratings. However, the conversion result in these cases will be
SC
= 5.0V, V
CC
+ 4 TCL)
conversion clock depend on the programming. Referring to Table 33 on page 135:
AGND
ain
can be charged/discharged by the external source. The internal resistance of
= 0V, V
CC
AREF
1 - 8
7
7
2 - 4
3 - 4
5
5
5
5
t
6 - 7
Test Condition
S
= 4.9V. It is guaranteed by design characterization for all other
in [ns]
OV
specification) occurs on maximum 2 not selected analog input
V
DD
2 - 7
+ 0.1V; V
4.0
V
–
–
–
–
48 TCL
388 TCL
-0.5
-1.5
-1.0
-2.0
–
–
minimum
S
AGND
sample time. After the end of the t
SS
0.1V V
Limit Values
s
sampling time of the ST10 ADC:
SC
V
V
500
1
10
15
1 536 TCL
2 884 TCL
+0.5
+1.5
+1.0
+2.0
(t
1/500
AREF
S
sample clock depend on the
DD
AGND
maximum
/ 150) - 0.25
+ 0.1
c
conversion time.
V
SS
+ 0.2V
S
Unit
LSB
LSB
LSB
LSB
sample
pF
pF
k
V
V
A
A