ST10F269-DPB STMicroelectronics, ST10F269-DPB Datasheet - Page 33

• Manufacturer Part Number: ST10F269-DPB
• Description: MCU 16BIT 256K FLASH 144PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F269-DPB

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-BFQFP
• Processor Series: ST10F26x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

5.6.5 - Choosing the Baud Rate for the BSL
The calculation of the serial Baud rate for ASC0
from the length of the first zero Byte that is
received, allows the operation of the bootstrap
loader of the ST10F269 with a wide range of Baud
rates. However, the upper and lower limits have to
be kept, in order to insure proper data transfer.
The ST10F269 uses timer T6 to measure the
length of the initial zero Byte. The quantization
uncertainty of this measurement implies the first
deviation from the real Baud rate, the next
deviation is implied by the computation of the
S0BRL reload value from the timer contents. The
formula below shows the association:
For a correct data transfer from the host to the
ST10F269 the maximum deviation between the
internal initialized Baud rate for ASC0 and the real
Baud rate of the host should be below 2.5%. The
deviation (F
and ST10F269 Baud rate can be calculated via
the formula below:
Figure 8 : Baud Rate Deviation Between Host and ST10F269
S0BRL
2.5%
F
B
F
B
ST10F269
B
=
B
F
Low
2.5 %
B
B
=
, in percent) between host Baud rate
B
------------------------------------------- -
C ontr
T6 36
------------------- -
=
72
B C ontr
–
–
B
----------------------------------------------- -
32
Ho st
,
T6
S0BRL
f
CPU
B
=
High
100
9
-- -
4
+
% ,
-----------------
B Host
1
f
CPU
I
II
Note: Function (F
This Baud rate deviation is a nonlinear function
depending on the CPU clock and the Baud rate of
the host. The maxima of the function (F
increase with the host Baud rate due to the
smaller Baud rate pre-scaler factors and the
implied higher quantization error (see Figure 8).
The minimum Baud rate (B
determined by the maximum count capacity of
timer T6, when measuring the zero Byte, and it
depends on the CPU clock. Using the maximum
T6 count 2
rate can be calculated. The lowest standard Baud
rate in this case would be 1200 Baud. Baud rates
below B
case ASC0 cannot be initialized properly.
The maximum Baud rate (B
is the highest Baud rate where the deviation still
does not exceed the limit, so all Baud rates
between B
limit. The maximum standard Baud rate that fulfills
this requirement is 19200 Baud.
Higher Baud rates, however, may be used as
long as the actual deviation does not exceed the
limit. A certain Baud rate (marked ’I’ in Figure 8)
may violate the deviation limit, while an even
higher Baud rate (marked ’II’ in Figure 8) stays
very well below it. This depends on the host
interface.
tolerances of oscillators and other devices
supporting the serial communication.
Low
Low
16
would cause T6 to overflow. In this
in the formula the minimum Baud
and B
B
High
) does not consider the
are below the deviation
Low
High
in the Figure 8) is
in the Figure 8)
ST10F269
B
HOST
33/160
B
)