ST10F269-DPB STMicroelectronics, ST10F269-DPB Datasheet - Page 113

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ST10F269-DPB

Manufacturer Part Number
ST10F269-DPB
Description
MCU 16BIT 256K FLASH 144PQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet

Specifications of ST10F269-DPB

Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-BFQFP
Processor Series
ST10F26x
Core
ST10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
ST10F269-DPB
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
ST10F269-DPB
Manufacturer:
ST
0
Figure 59 : Minimum External Reset Circuitry
Figure 60 : External Reset Hardware Circuitry
Table 29 : PORT0 Latched Configuration for the Different Resets
Table 30 : PORT0 Bits Latched into the Different Registers After Reset
Notes: 1. Not latched from PORT0.
PORT0 bit
BUSCON0
PORT0 bit
X : Pin is sampled
- : Pin is not sampled
Software Reset
Watchdog Reset
Short Hardware Reset
Long Hardware Reset
Power-On Reset
SYSCON
RP0H
Internal
Name
Logic
nber
Sample event
2. Only RP0H low byte is used and the bit-fields are latched from PORT0 high byte to RP0H low byte.
3. Indirectly depend on PORT0.
4. Bits set if EA pin is 1.
2
V
R0
C0
DD
V
R0
C0
CLKCFG CLKCFG CLKCFG SALSEL SALSEL CSSEL
DD
+
X
X
X
h7
1
1
1
+
To Clock Generator
X
X
X
h6
1
1
1
RPD
ST10F269
RPD
RSTOUT
ST10F269
X
X
X
h5
1
1
1
X
X
-
-
-
To Port 4 Logic
X
X
X
h4
X
X
-
-
-
1
1
1
RSTOUT
RSTIN
X
X
-
-
-
X
X
h3
RSTIN
-
1
1
X
X
X
X
X
ACT0
BUS
To Port 6 Logic
X
X
h2
V
1
1
DD
C1
4
X
X
X
X
X
BYTDIS
CSSEL
CTL0
+
ALE
X
h1
Open - drain
Inverter
1
X
X
X
X
X
4
b)
R2
3
WRC BUSTYP BUSTYP
X
X
X
h0
-
1
1
1
X
X
X
X
X
WRCFG
CLKCFG CLKCFG CLKCFG SALSEL SALSEL CSSEL CSSEL WRC
D2
a)
BTYP
X
I7
PORT0
X
X
X
X
X
1
Hardware
Hardware
3
External
External
a) Manual hardware reset1
b) For automatic power-up and
X
X
X
X
X
BTYP
interruptible power-down mode
X
X
I6
External
Reset Source
1
1
X
X
X
X
X
X
X
X
I5
R
D1
1
1
1
X
X
X
-
-
Internal
BSL
X
X
I4
X
X
X
1
1
-
-
+
V
R1
DD
C1
X
X
X
X
X
X
I3
-
-
R
1
1
1
X
X
X
-
-
X
X
X
I2
R
ST10F269
1
1
1
Internal Internal
X
X
X
-
-
ADP
113/160
X
X
I1
1
1
X
X
X
-
-
EMU
X
X
I0
1
1

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