MC908QB4MDTE Freescale Semiconductor, MC908QB4MDTE Datasheet - Page 187

• Manufacturer Part Number: MC908QB4MDTE
• Description: IC MCU 8BIT 4K FLASH 16-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QB4MDTE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-TSSOP
• Processor Series: HC08QB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: 3-Wire, ESCI, SPI, UART
• Number Of Programmable I/os: 13
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

CHxIE — Channel x Interrupt Enable Bit
MSxB — Mode Select Bit B
MSxA — Mode Select Bit A
Freescale Semiconductor
Writing a 1 to CHxF has no effect.
This read/write bit enables TIM interrupt service requests on channel x.
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TSC0 and
TSC2 registers.
Setting MS0B causes the contents of TSC1 to be ignored by the TIM and reverts TCH1 to
general-purpose I/O.
Setting MS2B causes the contents of TSC3 to be ignored by the TIM and reverts TCH3 to
general-purpose I/O.
When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output
compare/PWM operation. See
When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin (see
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
1 = Channel x interrupt requests enabled
0 = Channel x interrupt requests disabled
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
1 = Initial output level low
0 = Initial output level high
MSxB
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIM status and control register (TSC).
X
X
0
0
0
0
0
0
0
1
1
1
MSxA
X
X
X
0
1
0
0
0
1
1
1
1
Table 16-2. Mode, Edge, and Level Selection
ELSxB
0
0
0
1
1
0
0
1
1
0
1
1
Table
MC68HC908QB8 Data Sheet, Rev. 3
ELSxA
16-2.
0
0
1
0
1
0
1
0
1
1
0
1
Output compare
Buffered output
buffered PWM
NOTE
Output preset
Input capture
compare or
or PWM
Mode
Pin under port control; initial
output level high
Pin under port control; initial
output level low
Capture on rising edge only
Capture on falling edge only
Capture on rising or falling edge
Software compare only
Toggle output on compare
Clear output on compare
Set output on compare
Toggle output on compare
Clear output on compare
Set output on compare
Configuration
Table
Registers
16-2).
187