MC908JL8MPE Freescale Semiconductor, MC908JL8MPE Datasheet - Page 107

• Manufacturer Part Number: MC908JL8MPE
• Description: IC MCU 8K FLASH 8MHZ 28-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JL8MPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 13x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Processor Series: HC08JL
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 8-bit
• Controller Family/series: HC08
• No. Of I/o's: 23
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Addr.
$002A
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$0030
$0031
$0032
$0033
TIM1 Status and Control
TIM2 Status and Control
TIM1 Channel 0 Status
TIM1 Channel 1 Status
TIM1 Counter Register
TIM1 Counter Register
TIM2 Counter Register
TIM2 Counter Register
TIM1 Counter Modulo
TIM2 Counter Modulo
and Control Register
and Control Register
TIM Counter Modulo
Register Name
TIM1 Channel 0
TIM1 Channel 0
TIM1 Channel 1
TIM1 Channel 1
Register High
Register High
Register High
Register High
Register Low
Register Low
Register Low
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
(T2MODH)
(T1MODL)
(T1CNTH)
(T2CNTH)
(T1CH0H)
(T1CH1H)
(T1CNTL)
(T2CNTL)
(TMODH)
(T1CH0L)
(T1CH1L)
(T1SC0)
(T1SC1)
Register
Register
(T1SC)
(T2SC)
Figure 8-2. TIM I/O Register Summary (Sheet 1 of 2)
High
High
Low
Low
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Bit 15
Bit 15
CH0F
Bit 15
CH1F
Bit 15
Bit 15
Bit 15
Bit 7
TOF
Bit 7
Bit 7
Bit 7
Bit 7
TOF
Bit 7
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
= Unimplemented
CH0IE
CH1IE
TOIE
TOIE
14
14
14
14
14
14
6
0
0
6
0
1
6
1
0
6
0
6
0
0
6
0
1
TSTOP
TSTOP
MS0B
13
13
13
13
13
13
5
1
0
5
0
1
5
1
0
5
0
0
5
1
0
5
0
1
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
MS0A
MS1A
TRST
TRST
12
12
12
12
12
12
4
0
0
0
4
0
1
4
1
0
4
0
4
0
0
0
4
0
1
ELS0B
ELS1B
11
11
11
11
11
11
3
0
0
0
3
0
1
3
1
0
3
0
3
0
0
0
3
0
1
ELS0A
ELS1A
PS2
PS2
10
10
10
10
10
10
2
0
0
2
0
1
2
1
0
2
0
2
0
0
2
0
1
Functional Description
TOV0
TOV1
PS1
PS1
1
0
9
0
1
0
9
1
1
1
0
9
1
0
9
1
0
9
0
1
0
9
1
CH0MAX
CH1MAX
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
PS0
PS0
0
0
0
1
1
0
0
0
0
0
1
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