MC9S08RD32CDWE Freescale Semiconductor, MC9S08RD32CDWE Datasheet - Page 99

• Manufacturer Part Number: MC9S08RD32CDWE
• Description: IC MCU 32K FLASH 2K RAM 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08RD32CDWE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: S08RD
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08RG60E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
BRCLR n,opr8a,rel
BRN rel
BRSET n,opr8a,rel
BSET n,opr8a
BSR rel
CBEQ opr8a,rel
CBEQA #opr8i,rel
CBEQX #opr8i,rel
CBEQ oprx8,X+,rel
CBEQ ,X+,rel
CBEQ oprx8,SP,rel
CLC
CLI
CLR opr8a
CLRA
CLRX
CLRH
CLR oprx8,X
CLR ,X
CLR oprx8,SP
CMP #opr8i
CMP opr8a
CMP opr16a
CMP oprx16,X
CMP oprx8,X
CMP ,X
CMP oprx16,SP
CMP oprx8,SP
COM opr8a
COMA
COMX
COM oprx8,X
COM ,X
COM oprx8,SP
CPHX opr16a
CPHX #opr16i
CPHX opr8a
CPHX oprx8,SP
Source
Form
Branch if Bit n in Memory
Clear
Branch Never
Branch if Bit n in Memory
Set
Set Bit n in Memory
Branch to Subroutine
Compare and Branch if
Equal
Clear Carry Bit
Clear Interrupt Mask Bit
Clear
Compare Accumulator
with Memory
Complement
(One’s Complement)
Compare Index Register
(H:X) with Memory
Operation
Table 7-2. HCS08 Instruction Set Summary (Sheet 3 of 7)
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
push (PCH); SP ← (SP) – 0x0001
push (PCL); SP ← (SP) – 0x0001
(CCR Updated But Operands Not
(CCR Updated But Operands Not
(H:X) – (M:M + 0x0001)
M ← (M) = 0xFF – (M)
M ← (M) = 0xFF – (M)
M ← (M) = 0xFF – (M)
M ← (M)= 0xFF – (M)
A ← (A) = 0xFF – (A)
X ← (X) = 0xFF – (X)
PC ← (PC) + 0x0002
Uses 3 Bus Cycles
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (X) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (Mn) = 0
Branch if (Mn) = 1
PC ← (PC) + rel
Description
M ← 0x00
M ← 0x00
M ← 0x00
M ← 0x00
A ← 0x00
X ← 0x00
H ← 0x00
Changed)
Changed)
(A) – (M)
Mn ← 1
C ← 0
Central Processor Unit (S08CPUV2)Central Processor Unit (S08CPUV2)
I ← 0
– – – – –
– – – – – –
– – – – –
– – – – – –
– – – – – –
– – – – – –
– – – – – 0
– – 0 – – –
0 – – 0 1 –
0 – –
V H I N Z C
– –
– –
on CCR
Effect
1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
REL
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
REL
DIR
IMM
IMM
IX1+
IX+
SP1
INH
INH
DIR
INH
INH
INH
IX1
IX
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
DIR
INH
INH
IX1
IX
SP1
EXT
IMM
DIR
SP1
9ED1
9EE1
9E6F
9EF3
9E61
9E63
AD rr
0D
0C
1C
8C
C1
D1
0B
0A
0E
1A
1E
9A
A1
B1
E1
3E
01
03
05
07
09
0F
21 rr
00
02
04
06
08
10
12
14
16
18
31
41
51
61
71
98
3F
4F
5F
6F
7F
F1
33
43
53
63
73
65
75
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd
dd
dd
dd
dd
dd
dd
dd
dd rr
ii
ii
ff
rr
ff
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ee ff
ff
dd
ff
ff
hh ll
jj
dd
ff
rr
rr
rr
rr
kk
5
5
5
5
5
5
5
5
3
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
4
4
5
5
6
1
1
5
1
1
1
5
4
6
2
3
4
4
3
3
5
4
5
1
1
5
4
6
6
3
5
6
99