MC9S08RD32PE Freescale Semiconductor, MC9S08RD32PE Datasheet - Page 154

IC MCU 32K FLASH 2K RAM 28-DIP

MC9S08RD32PE

Manufacturer Part Number
MC9S08RD32PE
Description
IC MCU 32K FLASH 2K RAM 28-DIP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of MC9S08RD32PE

Core Processor
HCS08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-DIP (0.600", 15.24mm)
Processor Series
S08RD
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
39
Number Of Timers
2
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08RG60E
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S08RD32PE
Manufacturer:
Freescale Semiconductor
Quantity:
135
Serial Communications Interface (S08SCIV1)
154
RDRF
Field
IDLE
OR
NF
FE
PF
5
4
3
2
1
0
Receive Data Register Full Flag — RDRF becomes set when a character transfers from the receive shifter into
the receive data register (SCI1D). To clear RDRF, read SCI1S1 with RDRF = 1 and then read the SCI data
register (SCI1D).
0 Receive data register empty.
1 Receive data register full.
Idle Line Flag — IDLE is set when the SCI receive line becomes idle for a full character time after a period of
activity. When ILT = 0, the receiver starts counting idle bit times after the start bit. So if the receive character is
all 1s, these bit times and the stop bit time count toward the full character time of logic high (10 or 11 bit times
depending on the M control bit) needed for the receiver to detect an idle line. When ILT = 1, the receiver doesn’t
start counting idle bit times until after the stop bit. So the stop bit and any logic high bit times at the end of the
previous character do not count toward the full character time of logic high needed for the receiver to detect an
idle line.
To clear IDLE, read SCI1S1 with IDLE = 1 and then read the SCI data register (SCI1D). After IDLE has been
cleared, it cannot become set again until after a new character has been received and RDRF has been set. IDLE
will get set only once even if the receive line remains idle for an extended period.
0 No idle line detected.
1 Idle line was detected.
Receiver Overrun Flag — OR is set when a new serial character is ready to be transferred to the receive data
register (buffer), but the previously received character has not been read from SCI1D yet. In this case, the new
character (and all associated error information) is lost because there is no room to move it into SCI1D. To clear
OR, read SCI1S1 with OR = 1 and then read the SCI data register (SCI1D).
0 No overrun.
1 Receive overrun (new SCI data lost).
Noise Flag — The advanced sampling technique used in the receiver takes seven samples during the start bit
and three samples in each data bit and the stop bit. If any of these samples disagrees with the rest of the samples
within any bit time in the frame, the flag NF will be set at the same time as the flag RDRF gets set for the
character. To clear NF, read SCI1S1 and then read the SCI data register (SCI1D).
0 No noise detected.
1 Noise detected in the received character in SCI1D.
Framing Error Flag — FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop
bit was expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read
SCI1S1 with FE = 1 and then read the SCI data register (SCI1D).
0 No framing error detected. This does not guarantee the framing is correct.
1 Framing error.
Parity Error Flag — PF is set at the same time as RDRF when parity is enabled (PE = 1) and the parity bit in
the received character does not agree with the expected parity value. To clear PF, read SCI1S1 and then read
the SCI data register (SCI1D).
0 No parity error.
1 Parity error.
Table 12-5. SCI1S1 Register Field Descriptions (continued)
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Description
Freescale Semiconductor

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