MC908AP32ACFAE Freescale Semiconductor, MC908AP32ACFAE Datasheet - Page 37

• Manufacturer Part Number: MC908AP32ACFAE
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AP32ACFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SCI, SPI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: HC08AP
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908AP64E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
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Addr.
ADC Clock Control Register
Timebase Control Register
MMIIC CRC Data Register
ADC Data Register High 0
MMIIC Frequency Divider
ADC Status and Control
Register Name
MMIIC Data Receive
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
U = Unaffected
(MMCRDR)
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 9)
(MMDRR)
(MMFDR)
Reserved
(ADICLK)
(ADSCR)
(ADRH0)
Register
Register
Register
(TBCR)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read: MMCRCD7 MMCRCD6 MMCRCD5 MMCRCD4 MMCRCD3 MMCRCD2 MMCRCD1 MMCRCD0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
MC68HC908AP A-Family Data Sheet, Rev. 3
X = Indeterminate
MMRD7
COCO
ADIV2
Bit 7
TBIF
ADx
R
R
0
0
0
0
0
0
0
0
MMRD6
ADIV1
TBR2
AIEN
ADx
R
R
6
0
0
0
0
0
0
0
0
MMRD5
ADCO
ADIV0
TBR1
ADx
R
R
5
0
0
0
0
0
0
0
0
= Unimplemented
ADICLK
MMRD4
ADCH4
TBR0
ADx
R
R
4
0
0
0
0
1
0
0
0
MODE1
MMRD3
ADCH3
TACK
ADx
R
R
3
0
0
0
0
0
1
0
0
0
MMBR2
MODE0
MMRD2
ADCH2
TBIE
ADx
R
R
R
2
0
0
1
0
1
0
0
= Reserved
MMBR1
MMRD1
ADCH1
TBON
ADx
R
R
1
0
0
0
0
1
0
0
0
Monitor ROM
MMBR0
MMRD0
ADCH0
Bit 0
ADx
R
R
R
R
0
0
0
0
1
0
0
0
37