MC9S08GB60ACFUE Freescale Semiconductor, MC9S08GB60ACFUE Datasheet - Page 39

• Manufacturer Part Number: MC9S08GB60ACFUE
• Description: IC MCU 60K FLASH 4K RAM 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GB60ACFUE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: S08GB
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 8
• Operating Supply Voltage: 0 V to 1.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: M68EVB908GB60E, M68DEMO908GB60E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.6.4
Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set.
This register is described in the
is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain
active when the MCU enters stop mode so background debug communication is still possible. In addition,
the voltage regulator does not enter its low-power standby state but maintains full internal regulation. If
the user attempts to enter either stop1 or stop2 with ENBDM set, the MCU will instead enter stop3.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or wait
mode. The BACKGROUND command can be used to wake the MCU from stop and enter active
background mode if the ENBDM bit is set. After the device enters background debug mode, all
background commands are available. The table below summarizes the behavior of the MCU in stop when
entry into the background debug mode is enabled.
1
2
3.6.5
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop by setting the LVDE and the LVDSE bits in SPMSC1 when
the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode. If the
user attempts to enter either stop1 or stop2 with the LVD enabled for stop (LVDSE = 1), the MCU will
instead enter stop3. The table below summarizes the behavior of the MCU in stop when the LVD is
enabled.
1
3.6.6
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,
Freescale Semiconductor
Mode
Stop3
Mode
Stop3
The 1 kHz internal RTI clock is not available in stop3 with active BDM enabled.
Either ATD stop mode or power-down mode depending on the state of ATDPU.
Either ATD stop mode or power-down mode depending on the state of ATDPU.
Don’t
Don’t
PDC
PDC
care
care
Active BDM Enabled in Stop Mode
LVD Enabled in Stop Mode
On-Chip Peripheral Modules in Stop Modes
PPDC
PPDC
Don’t
Don’t
care
care
Peripherals,
Peripherals,
CPU, Digital
CPU, Digital
Standby
Standby
Flash
Flash
Table 3-2. BDM Enabled Stop Mode Behavior
Table 3-3. LVD Enabled Stop Mode Behavior
Chapter 15, “Development
MC9S08GB60A Data Sheet, Rev. 2
Standby
Standby
RAM
RAM
Standby
Active
ICG
ICG
Support,” section of this data sheet. If ENBDM
Disabled
Disabled
ATD
ATD
2
1
Regulator
Regulator
Active
Active
Chapter 3 Modes of Operation
States held Optionally on
States held Optionally on
I/O Pins
I/O Pins
RTI
RTI
1
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