MC9S12XA256CAL Freescale Semiconductor, MC9S12XA256CAL Datasheet - Page 701

• Manufacturer Part Number: MC9S12XA256CAL
• Description: IC MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA256CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 16 Channel)
• Package: 112LQFP
• Family Name: HCS12
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.3.1.5
Read: Anytime when unlocked and not secured and not armed.
Write: Aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer
contents
Freescale Semiconductor
0x0024
0x0025
Bit[15:0]
Reset
Reset
Field
15–0
W
W
R
R
Bit 15
Bit 7
Trace Buffer Data Bits — The trace buffer register is a window through which the 64-bit wide data lines of the
trace buffer may be read 16 bits at a time. Each valid read of DBGTB increments an internal trace buffer pointer
which points to the next address to be read. When the ARM bit is written to 1 the trace buffer is locked to prevent
reading. The trace buffer can only be unlocked for reading by writing to DBGTB with an aligned word write when
the module is disarmed. The DBGTB register can be read only as an aligned word, any byte reads or misaligned
access of these registers will return 0 and will not cause the trace buffer pointer to increment to the next trace
buffer address. The same is true for word reads while the debugger is armed. System resets do not affect the
trace buffer contents. The POR state is undefined.
Debug Trace Buffer Register (DBGTBH:DBGTBL)
15
CDCM
ABCM
X
X
7
00
01
10
11
00
01
10
11
Match2 mapped to comparator C match....... Match3 mapped to comparator D match.
Match0 mapped to comparator A match....... Match1 mapped to comparator B match.
14
14
X
6
X
6
Figure 19-7. Debug Trace Buffer Register (DBGTBH)
Figure 19-8. Debug Trace Buffer Register (DBGTBL)
Match 0 mapped to comparator A/B outside range....... Match1 disabled.
Match2 mapped to comparator C/D outside range....... Match3 disabled.
Match 0 mapped to comparator A/B inside range....... Match1 disabled.
Match2 mapped to comparator C/D inside range....... Match3 disabled.
Table 19-16. DBGTB Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
13
13
X
X
5
Table 19-14. CDCM Encoding
Table 19-15. ABCM Encoding
5
12
12
X
4
X
4
Description
Description
Description
Reserved
Reserved
11
11
X
X
3
3
Chapter 19 S12X Debug (S12XDBGV2) Module
10
10
X
X
2
2
X
X
9
1
9
1
Bit 8
Bit 0
X
X
8
0
703