MC9S12XA256CAL Freescale Semiconductor, MC9S12XA256CAL Datasheet - Page 911

• Manufacturer Part Number: MC9S12XA256CAL
• Description: IC MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA256CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 16 Channel)
• Package: 112LQFP
• Family Name: HCS12
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.0.5
Table 23-3
level (IO), reduced drive (RDR), pull enable (PE), pull select (PS), and interrupt enable (IE) for the
ports.
The configuration bit PS is used for two purposes:
1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled.
2. Select either a pull-up or pull-down device if PE is active.
Address
0x026C
0x026D
0x027C
0x027D
0x026B
0x026E
0x026F
0x027A
0x027B
0x027E
0x027F
0x0270
0x0271
0x0272
0x0273
0x0274
0x0275
0x0276
0x0277
0x0278
0x0279
1. Write access not applicable for one or more register bits. Refer to
summarizes the effect on the various configuration bits, data direction (DDR), output
Register Descriptions
ter
Descriptions”.
Port J Reduced Drive Register (RDRJ)
Port J Pull Device Enable Register (PERJ)
Port J Polarity Select Register (PPSJ)
Port J Interrupt Enable Register (PIEJ)
Port J Interrupt Flag Register (PIFJ)
PIM Reserved
Port AD0 Data Register 1 (PT1AD0)
PIM Reserved
Port AD0 Data Direction Register 1 (DDR1AD0)
PIM Reserved
Port AD0 Reduced Drive Register 1 (RDR1AD0)
PIM Reserved
Port AD0 Pull Up Enable Register 1 (PER1AD0)
Port AD1 Data Register 0 (PT0AD1)
Port AD1 Data Register 1 (PT1AD1)
Port AD1 Data Direction Register 0 (DDR0AD1)
Port AD1 Data Direction Register 1 (DDR1AD1)
Port AD1 Reduced Drive Register 0 (RDR0AD1)
Port AD1 Reduced Drive Register 1 (RDR1AD1)
Port AD1 Pull Up Enable Register 0 (PER0AD1)
Port AD1 Pull Up Enable Register 1 (PER1AD1)
Table 23-2. PIM Memory Map (Sheet 3 of 3)
Use
Section 23.0.5, “Regis-
Read / Write
Read / Write
Read / Write
Read / Write
Read / Write
Read / Write
Read / Write
Read / Write
Read / Write
Read / Write
Read / Write
Read / Write
Read / Write
Read / Write
Read / Write
Read / Write
Read / Write
Access
—
—
—
—
1
1
1
1
1