C8051F016-GQR Silicon Laboratories Inc, C8051F016-GQR Datasheet - Page 120

• Manufacturer Part Number: C8051F016-GQR
• Description: IC 8051 MCU 32K FLASH 48TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F01xr

Specifications of C8051F016-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.6.3. Data Register
The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received.
Data remains stable in the register as long as SI is set to logic 1. Software can safely read or write to the data
register when the SI flag is set. Software should not attempt to access the SMB0DAT register when the SMBus is
enabled and the SI flag is cleared to logic 0 since the hardware may be in the process of shifting a byte of data in or
out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received data is
located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously being shifted
in. Therefore, SMB0DAT always contains the last data byte present on the bus. Thus, in the event of lost arbitration,
the transition from master transmitter to slave receiver is made with the correct data in SMB0DAT.
16.6.4. Address Register
The SMB0ADR Address register holds the slave address for the SMBus interface. In slave mode, the seven most-
significant bits hold the 7-bit slave address. The least significant bit, bit 0, is used to enable the recognition of the
general call address (0x00). If bit 0 is set to logic 1, the general call address will be recognized. Otherwise, the
general call address is ignored. The contents of this register are ignored when the SMBus hardware is operating in
master mode.
Bits7-0: SMB0DAT: SMBus Data.
Bits7-1: SLV6-SLV0: SMBus Slave Address.
Bit0:
SLV6
R/W
R/W
Bit7
Bit7
The SMB0DAT register contains a byte of data to be transmitted on the SMBus serial
interface or a byte that has just been received on the SMBus serial interface. The CPU can
read from or write to this register whenever the SI serial interrupt flag (SMB0CN.3) is set
to logic one. The serial data in the register remains stable as long as the SI flag is set.
When the SI flag is not set, the system may be in the process of shifting data in/out and the
CPU should not attempt to access this register.
These bits are loaded with the 7-bit slave address to which the SMBus will respond when
operating as a slave transmitter or slave receiver. SLV6 is the most significant bit of the
address and corresponds to the first bit of the address byte received on the SMBus.
This bit is used to enable general call address (0x00) recognition.
0: General call address is ignored.
1: General call address is recognized.
GC: General Call Address Enable.
SLV5
R/W
R/W
Bit6
Bit6
Figure 16.7. SMB0ADR: SMBus Address Register
Figure 16.6. SMB0DAT: SMBus Data Register
SLV4
R/W
R/W
Bit5
Bit5
SLV3
R/W
R/W
Bit4
Bit4
Rev. 1.7
SLV2
R/W
R/W
Bit3
Bit3
SLV1
R/W
R/W
Bit2
Bit2
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
SLV0
R/W
R/W
Bit1
Bit1
R/W
R/W
Bit0
Bit0
GC
SFR Address:
SFR Address:
Reset Value
Reset Value
00000000
00000000
0xC2
0xC3
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