C8051F016-GQR Silicon Laboratories Inc, C8051F016-GQR Datasheet - Page 167

• Manufacturer Part Number: C8051F016-GQR
• Description: IC 8051 MCU 32K FLASH 48TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F01xr

Specifications of C8051F016-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.2.
The Flash memory can be programmed directly over the JTAG interface using the Flash Control, Flash Data, Flash
Address, and Flash Scale registers. These Indirect Data Registers are accessed via the JTAG Instruction Register.
Read and write operations on indirect data registers are performed by first setting the appropriate DR address in the
IR register. Each read or write is then initiated by writing the appropriate Indirect Operation Code (IndOpCode) to
the selected data register. Incoming commands to this register have the following format:
IndOpCode: These bit set the operation to perform according to the following table:
The Poll operation is used to check the Busy bit as described below. Although a Capture-DR is performed, no
Update-DR is allowed for the Poll operation. Since updates are disabled, polling can be accomplished by shifting
in/out a single bit.
The Read operation initiates a read from the register addressed by the IR. Reads can be initiated by shifting only 2
bits into the indirect register. After the read operation is initiated, polling of the Busy bit must be performed to
determine when the operation is complete.
The write operation initiates a write of WriteData to the register addressed by the IR. Registers of any width up to
18 bits can be written. If the register to be written contains fewer than 18 bits, the data in WriteData should be left-
justified, i.e. its MSB should occupy bit 17 above. This allows shorter registers to be written in fewer JTAG clock
cycles. For example, an 8-bit register could be written by shifting only 10 bits. After a Write is initiated, the Busy
bit should be polled to determine when the next operation can be initiated. The contents of the Instruction Register
should not be altered while either a read or write operation is in progress.
Outgoing data from the indirect Data Register has the following format:
The Busy bit indicates that the current operation is not complete. It goes high when an operation is initiated and
returns low when complete. Read and Write commands are ignored while Busy is high. In fact, if polling for Busy
to be low will be followed by another read or write operation, JTAG writes of the next operation can be made while
checking for Busy to be low. They will be ignored until Busy is read low, at which time the new operation will
initiate. This bit is placed at bit 0 to allow polling by single-bit shifts. When waiting for a Read to complete and
Busy is 0, the following 18 bits can be shifted out to obtain the resulting data. ReadData is always right-justified.
This allows registers shorter than 18 bits to be read using a reduced number of shifts. For example, the result from a
byte-read requires 9 bit shifts (Busy + 8 bits).
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C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
IndOpCode
Flash Programming Commands
19:18
19
0
IndOpCode
0x
10
11
Rev. 1.7
WriteData
Operation
ReadData
Write
17:0
Read
18:1
Poll
Busy
0