C8051F016-GQR Silicon Laboratories Inc, C8051F016-GQR Datasheet - Page 75

• Manufacturer Part Number: C8051F016-GQR
• Description: IC 8051 MCU 32K FLASH 48TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F01xr

Specifications of C8051F016-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

75
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Bit7:
Bit6:
Bit5:
Bits4-3: RS1-RS0: Register Bank Select.
Bit2:
Bit1:
Bit0:
R/W
Bit7
CY
This bit is set when the last arithmetic operation results in a carry (addition) or a borrow
(subtraction). It is cleared to 0 by all other arithmetic operations.
This bit is set when the last arithmetic operation results in a carry into (addition) or a
borrow from (subtraction) the high order nibble. It is cleared to 0 by all other arithmetic
operations.
This is a bit-addressable, general purpose flag for use under software control.
These bits select which register bank is used during register accesses.
Note: Any instruction which changes the RS1-RS0 bits must not be immediately followed
by the “MOV Rn, A” instruction.
This bit is set to 1 under the following circumstances:
This is a bit-addressable, general purpose flag for use under software control.
(Read only)
This bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the
sum is even.
CY: Carry Flag.
AC: Auxiliary Carry Flag.
F0: User Flag 0.
OV: Overflow Flag.
F1: User Flag 1.
PARITY: Parity Flag.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all
other cases.
 A DIV instruction causes a divide-by-zero condition.
 An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
 A MUL instruction results in an overflow (result is greater than 255) .
RS1
0
0
1
1
R/W
Bit6
AC
RS0
0
1
0
1
Figure 10.6. PSW: Program Status Word
R/W
Bit5
F0
Register Bank
0
1
2
3
R/W
RS1
Bit4
0x00-0x07
0x08-0x0F
0x10-0x17
0x18-0x1F
Address
Rev. 1.7
RS0
R/W
Bit3
R/W
Bit2
OV
R/W
Bit1
F1
(bit addressable)
PARITY
R/W
Bit0
0xD0
SFR Address:
Reset Value
00000000