C8051F016-GQR Silicon Laboratories Inc, C8051F016-GQR Datasheet - Page 51

• Manufacturer Part Number: C8051F016-GQR
• Description: IC 8051 MCU 32K FLASH 48TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F01xr

Specifications of C8051F016-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7. DACs, 12 BIT VOLTAGE MODE
The C8051F000 MCU family has two 12-bit voltage-mode Digital to Analog Converters. Each DAC has an output
swing of 0V to VREF-1LSB for a corresponding input code range of 0x000 to 0xFFF. Using DAC0 as an example,
the 12-bit data word is written to the low byte (DAC0L) and high byte (DAC0H) data registers. Data is latched into
DAC0 after a write to the corresponding DAC0H register, so the write sequence should be DAC0L followed by
DAC0H if the full 12-bit resolution is required. The DAC can be used in 8-bit mode by initializing DAC0L to the
desired value (typically 0x00), and writing data to only DAC0H with the data shifted to the left. DAC0 Control
Register (DAC0CN) provides a means to enable/disable DAC0 and to modify its input data formatting.
The DAC0 enable/disable function is controlled by the DAC0EN bit (DAC0CN.7). Writing a 1 to DAC0EN
enables DAC0 while writing a 0 to DAC0EN disables DAC0. While disabled, the output of DAC0 is maintained in
a high-impedance state, and the DAC0 supply current falls to 1A or less. Also, the Bias Enable bit (BIASE) in the
REF0CN register (see Figure 9.2) must be set to 1 in order to supply bias to DAC0. The voltage reference for
DAC0 must also be set properly (see Section 9).
In some instances, input data should be shifted prior to a DAC0 write operation to properly justify data within the
DAC input registers. This action would typically require one or more load and shift operations, adding software
overhead and slowing DAC throughput. To alleviate this problem, the data-formatting feature provides a means for
the user to program the orientation of the DAC0 data word within data registers DAC0H and DAC0L. The three
DAC0DF bits (DAC0CN.[2:0]) allow the user to specify one of five data word orientations as shown in the
DAC0CN register definition.
DAC1 is functionally the same as DAC0 described above. The electrical specifications for both DAC0 and DAC1
are given in Table 7.1.
51
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
DAC0DF2
DAC0DF1
DAC0DF0
DAC1DF2
DAC1DF1
DAC1DF0
DAC0EN
DAC1EN
Figure 7.1. DAC Functional Block Diagram
8
8
8
8
12
12
Rev. 1.7
REF
REF
DAC0
DAC1
+
-
+
-
AGND
AGND
AV+
AV+
DAC0
DAC1