M30622F8PFP#D5C Renesas Electronics America, M30622F8PFP#D5C Datasheet - Page 27

IC M16C MCU FLASH 64K 100-QFP

M30622F8PFP#D5C

Manufacturer Part Number
M30622F8PFP#D5C
Description
IC M16C MCU FLASH 64K 100-QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheet

Specifications of M30622F8PFP#D5C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ03B0001-0241
1.6
Table 1.17
I : Input
Power Supply : Power supplies which relate to the external bus pins are separated as VCC2, thus they can be
NOTES:
Power supply
input
Analog power
supply input
Reset input
CNVSS
External data
bus width
select input
Bus control
pins
Signal Name
1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.
2. In M16C/62PT, apply 4.0 to 5.5 V to the VCC1 and VCC2 pins. Also the apply condition is that VCC1 = VCC2.
3. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked.
4. Bus control pins in M16C/62PT cannot be used.
(4)
Pin Description
Jan 10, 2006
O : Output
interfaced using the different voltage as VCC1.
Pin Description (100-pin and 128-pin Version) (1)
VCC1,VCC2
VSS
AVCC
AVSS
RESET
CNVSS
BYTE
D0 to D7
D8 to D15
A0 to A19
A0/D0 to
A7/D7
A1/D0 to
A8/D7
CS0 to CS3
WRL/WR
WRH/BHE
RD
ALE
HOLD
HLDA
RDY
Pin Name
I/O : Input and output
Page 25 of 96
Type
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
I
I
I
I
I
I
I
Supply
Power
VCC1
VCC1
VCC1
VCC1
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
(3)
Apply 2.7 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS
pin. The VCC apply condition is that VCC1 ≥ VCC2.
Applies the power supply for the A/D converter. Connect the AVCC
pin to VCC1. Connect the AVSS pin to VSS.
The microcomputer is in a reset state when applying “L” to the this pin.
Switches processor mode. Connect this pin to VSS to when after
a reset to start up in single-chip mode. Connect this pin to VCC1 to
start up in microprocessor mode.
Switches the data bus in external memory space. The data bus is
16 bits long when the this pin is held "L" and 8 bits long when the
this pin is held "H". Set it to either one. Connect this pin to VSS
when an single-chip mode.
Inputs and outputs data (D0 to D7) when these pins are set as the
separate bus.
Inputs and outputs data (D8 to D15) when external 16-bit data bus
is set as the separate bus.
Output address bits (A0 to A19).
Input and output data (D0 to D7) and output address bits (A0 to A7) by
timesharing when external 8-bit data bus are set as the multiplexed bus.
Input and output data (D0 to D7) and output address bits (A1 to A8)
by timesharing when external 16-bit data bus are set as the
multiplexed bus.
Output CS0 to CS3 signals. CS0 to CS3 are chip-select signals to
specify an external space.
Output WRL, WRH, (WR, BHE), RD signals. WRL and WRH or
BHE and WR can be switched by program.
• WRL, WRH and RD are selected
The WRL signal becomes "L" by writing data to an even address in
an external memory space.
The WRH signal becomes "L" by writing data to an odd address in
an external memory space.
The RD pin signal becomes "L" by reading data in an external
memory space.
• WR, BHE and RD are selected
The WR signal becomes "L" by writing data in an external memory space.
The RD signal becomes "L" by reading data in an external memory space.
The BHE signal becomes "L" by accessing an odd address.
Select WR, BHE and RD for an external 8-bit data bus.
ALE is a signal to latch the address.
While the HOLD pin is held "L", the microcomputer is placed in a
hold state.
In a hold state, HLDA outputs a "L" signal.
While applying a "L" signal to the RDY pin, the microcomputer is
placed in a wait state.
Description
(1, 2)
1. Overview

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