IC M16C MCU FLASH 64K 100-QFP

M30622F8PFP#D5C

Manufacturer Part NumberM30622F8PFP#D5C
DescriptionIC M16C MCU FLASH 64K 100-QFP
ManufacturerRenesas Electronics America
SeriesM16C™ M16C/60
M30622F8PFP#D5C datasheet
 


Specifications of M30622F8PFP#D5C

Core ProcessorM16C/60Core Size16-Bit
Speed24MHzConnectivityI²C, IEBus, UART/USART
PeripheralsDMA, WDTNumber Of I /o85
Program Memory Size64KB (64K x 8)Program Memory TypeFLASH
Ram Size4K x 8Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 V
Data ConvertersA/D 26x10b; D/A 2x8bOscillator TypeInternal
Operating Temperature-20°C ~ 85°CPackage / Case100-QFP
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantEeprom Size-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Page 51
52
Page 52
53
Page 53
54
Page 54
55
Page 55
56
Page 56
57
Page 57
58
Page 58
59
Page 59
60
Page 60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
Page 56/103

Download datasheet (2Mb)Embed
PrevNext
M16C/62P Group (M16C/62P, M16C/62PT)
Switching Characteristics
(V
= V
= 5V, V
= 0V, at T
CC1
CC2
SS
Table 5.28
Memory Expansion and Microprocessor Modes (for 1- to 3-wait setting and external
area access)
Symbol
t
Address Output Delay Time
d(BCLK-AD)
t
Address Output Hold Time (in relation to BCLK)
h(BCLK-AD)
t
Address Output Hold Time (in relation to RD)
h(RD-AD)
t
Address Output Hold Time (in relation to WR)
h(WR-AD)
t
Chip Select Output Delay Time
d(BCLK-CS)
t
Chip Select Output Hold Time (in relation to BCLK)
h(BCLK-CS)
t
ALE Signal Output Delay Time
d(BCLK-ALE)
t
ALE Signal Output Hold Time
h(BCLK-ALE)
t
RD Signal Output Delay Time
d(BCLK-RD)
t
RD Signal Output Hold Time
h(BCLK-RD)
t
WR Signal Output Delay Time
d(BCLK-WR)
t
WR Signal Output Hold Time
h(BCLK-WR)
t
Data Output Delay Time (in relation to BCLK)
d(BCLK-DB)
t
Data Output Hold Time (in relation to BCLK)
h(BCLK-DB)
t
Data Output Delay Time (in relation to WR)
d(DB-WR)
th(WR-DB)
Data Output Hold Time (in relation to WR)
t
HLDA Output Delay Time
d(BCLK-HLDA)
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
(
) x10
n 0.5
[
]
----------------------------------- - 40 ns
(
)
f BCLK
2. Calculated according to the BCLK frequency as follows:
9
0.5x10
[
]
----------------------- - 10 ns
(
)
f BCLK
3. This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = − CR X ln (1 − V
/ V
OL
CC2
by a circuit of the right figure.
For example, when V
= 0.2V
OL
of output ”L” level is
t = − 30pF X 1k Ω X In(1 − 0.2V
= 6.7ns.
Rev.2.41
Jan 10, 2006
Page 54 of 96
REJ03B0001-0241
= −20 to 85°C / −40 to 85°C unless otherwise specified)
opr
Parameter
(3)
(3)
n is “1” for 1-wait setting, “2” for 2-wait setting
and “3” for 3-wait setting.
(BCLK) is 12.5MHz or less.
)
, C = 30pF, R = 1k Ω , hold time
CC2
/ V
)
CC2
CC2
5. Electrical Characteristics
V
=V
CC1
CC2
Standard
Min.
Max.
25
4
0
(NOTE 2)
25
4
15
-4
See
25
Figure 5.2
0
25
0
40
4
(NOTE 1)
(NOTE 2)
40
R
DBi
C
=5V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns