M30622F8PFP#D5C Renesas Electronics America, M30622F8PFP#D5C Datasheet - Page 56

IC M16C MCU FLASH 64K 100-QFP

M30622F8PFP#D5C

Manufacturer Part Number
M30622F8PFP#D5C
Description
IC M16C MCU FLASH 64K 100-QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheet

Specifications of M30622F8PFP#D5C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
M16C/62P Group (M16C/62P, M16C/62PT)
Switching Characteristics
(V
= V
= 5V, V
= 0V, at T
CC1
CC2
SS
Table 5.28
Memory Expansion and Microprocessor Modes (for 1- to 3-wait setting and external
area access)
Symbol
t
Address Output Delay Time
d(BCLK-AD)
t
Address Output Hold Time (in relation to BCLK)
h(BCLK-AD)
t
Address Output Hold Time (in relation to RD)
h(RD-AD)
t
Address Output Hold Time (in relation to WR)
h(WR-AD)
t
Chip Select Output Delay Time
d(BCLK-CS)
t
Chip Select Output Hold Time (in relation to BCLK)
h(BCLK-CS)
t
ALE Signal Output Delay Time
d(BCLK-ALE)
t
ALE Signal Output Hold Time
h(BCLK-ALE)
t
RD Signal Output Delay Time
d(BCLK-RD)
t
RD Signal Output Hold Time
h(BCLK-RD)
t
WR Signal Output Delay Time
d(BCLK-WR)
t
WR Signal Output Hold Time
h(BCLK-WR)
t
Data Output Delay Time (in relation to BCLK)
d(BCLK-DB)
t
Data Output Hold Time (in relation to BCLK)
h(BCLK-DB)
t
Data Output Delay Time (in relation to WR)
d(DB-WR)
th(WR-DB)
Data Output Hold Time (in relation to WR)
t
HLDA Output Delay Time
d(BCLK-HLDA)
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
(
) x10
n 0.5
[
]
----------------------------------- - 40 ns
(
)
f BCLK
2. Calculated according to the BCLK frequency as follows:
9
0.5x10
[
]
----------------------- - 10 ns
(
)
f BCLK
3. This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = − CR X ln (1 − V
/ V
OL
CC2
by a circuit of the right figure.
For example, when V
= 0.2V
OL
of output ”L” level is
t = − 30pF X 1k Ω X In(1 − 0.2V
= 6.7ns.
Rev.2.41
Jan 10, 2006
Page 54 of 96
REJ03B0001-0241
= −20 to 85°C / −40 to 85°C unless otherwise specified)
opr
Parameter
(3)
(3)
n is “1” for 1-wait setting, “2” for 2-wait setting
and “3” for 3-wait setting.
(BCLK) is 12.5MHz or less.
)
, C = 30pF, R = 1k Ω , hold time
CC2
/ V
)
CC2
CC2
5. Electrical Characteristics
V
=V
CC1
CC2
Standard
Min.
Max.
25
4
0
(NOTE 2)
25
4
15
-4
See
25
Figure 5.2
0
25
0
40
4
(NOTE 1)
(NOTE 2)
40
R
DBi
C
=5V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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