MCF5232CAB80 Freescale Semiconductor, MCF5232CAB80 Datasheet - Page 38

IC MPU 32BIT COLDF 80MHZ 160-QFP

MCF5232CAB80

Manufacturer Part Number
MCF5232CAB80
Description
IC MPU 32BIT COLDF 80MHZ 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF523xr
Datasheet

Specifications of MCF5232CAB80

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
61
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Maximum Clock Frequency
80 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Program Memory Size
8KB
Cpu Speed
80MHz
Embedded Interface Type
I2C, SPI, UART
Digital Ic Case Style
QFP
No. Of Pins
160
Supply Voltage Range
1.4V To 1.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5232CAB80
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Electrical Characteristics
7.10
MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.
7.10.1
The receiver functions correctly up to a ERXCLK maximum frequency of 25 MHz +1%. The processor
clock frequency must exceed twice the ERXCLK frequency.
Table 18
Figure 19
38
I2C_SDA
I2C_SCL
Num
M1
M2
M3
M4
lists MII receive channel timings.
Fast Ethernet AC Timing Specifications
shows MII receive signal timings listed in
ERXD[3:0] (inputs)
MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER, and
ERXCLK)
ERXCLK (input)
ERXD[3:0], ERXDV, ERXER to ERXCLK setup
ERXCLK to ERXD[3:0], ERXDV, ERXER hold
ERXCLK pulse width high
ERXCLK pulse width low
I1
ERXER
ERXDV
MCF523x Integrated Microprocessor Hardware Specification, Rev. 4
I2
Figure 19. MII Receive Signal Timing Diagram
I4
Characteristic
Figure 18. I
Table 18. MII Receive Signal Timing
M1
I6
2
M2
C Input/Output Timings
M3
I7
Table
18.
I8
M4
35%
35%
Min
5
5
I5
65%
65%
Max
I3
Freescale Semiconductor
ERXCLK period
ERXCLK period
I9
Unit
ns
ns

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