HD6473308RCP10V Renesas Electronics America, HD6473308RCP10V Datasheet
HD6473308RCP10V
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HD6473308RCP10V Summary of contents
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To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April ...
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HITACHI SINGLE-CHIP MICROCOMPUTER HD6473308, HD6433308, HD6413308 HARDWARE MANUAL H8/330 ...
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The H8/330 is a high-performance single-chip microcomputer ideally suited for embedded control of industrial equipment. Its core is the H8/300 CPU: a high-speed processor. On-chip supporting modules provide memory, I/O, and timer functions, including: • 16K bytes of on-chip ROM ...
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Section 1. Overview ............................................................................................................... 1.1 Block Diagram...................................................................................................................... 1.2 Descriptions of Blocks.......................................................................................................... 1.3 Pin Assignments and Functions............................................................................................ 1.3.1 Pin Arrangement...................................................................................................... 1.3.2 Pin Functions ........................................................................................................... Section 2. MCU Operating Modes and Address Space 2.1 Overview............................................................................................................................... 17 2.2 Mode Descriptions................................................................................................................ 18 2.3 Address ...
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Block Data Transfer Instruction .............................................................................. 50 3.6 CPU States ............................................................................................................................ 51 3.6.1 Program Execution State ......................................................................................... 52 3.6.2 Exception-Handling State........................................................................................ 52 3.6.3 Power-Down State ................................................................................................... 53 3.7 Access Timing and Bus Cycle .............................................................................................. 53 3.7.1 Access to On-Chip Memory ...
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Free-Running Counter (FRC) – H'FF92.................................................................. 126 6.2.2 Output Compare Registers A and B (OCRA and OCRB) – H'FF94....................... 127 6.2.3 Input Capture Registers (ICRA to ICRD) – H'FF98, H'FF9A, H'FF9C, H'FF9E ......................................................................... 127 6.2.4 Timer Interrupt ...
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Section 8. PWM Timers 8.1 Overview............................................................................................................................... 171 8.1.1 Features.................................................................................................................... 171 8.1.2 Block Diagram......................................................................................................... 171 8.1.3 Input and Output Pins .............................................................................................. 172 8.1.4 Register Configuration ............................................................................................ 172 8.2 Register Descriptions............................................................................................................ 172 8.2.1 Timer Counter (TCNT) – H'FFA2 (PWM0), H'FFA6 (PWM1).............................. 172 ...
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Section 10. A/D Converter 10.1 Overview............................................................................................................................... 207 10.1.1 Features.................................................................................................................... 207 10.1.2 Block Diagram......................................................................................................... 208 10.1.3 Input Pins................................................................................................................. 209 10.1.4 Register Configuration ............................................................................................ 209 10.2 Register Descriptions............................................................................................................ 210 10.2.1 A/D Data Registers (ADDR) – H'FFE0 to H'FFE6................................................. 210 10.2.2 A/D Control/Status ...
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Operation .............................................................................................................................. 240 12.4.1 Expanded Modes (Modes 1 and 2) .......................................................................... 240 12.4.2 Single-Chip Mode (Mode 3) ................................................................................... 240 Section 13. ROM ....................................................................................................................... 241 13.1 Overview............................................................................................................................... 241 13.1.1 Block Diagram......................................................................................................... 242 13.2 PROM Mode......................................................................................................................... 242 13.2.1 PROM Mode Setup ...
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Block Diagram......................................................................................................... 265 16.2 Oscillator Circuit................................................................................................................... 265 16.3 System Clock Divider........................................................................................................... 268 Section 17. Electrical Specifications 17.1 Absolute Maximum Ratings ................................................................................................. 269 17.2 Electrical Characteristics ...................................................................................................... 269 17.2.1 DC Characteristics................................................................................................... 269 17.2.2 AC Characteristics................................................................................................... 273 17.2.3 A/D Converter Characteristics................................................................................. ...
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Table Table 1-1 Product Lineup ...................................................................................................... Table 1-2 Pin Assignments in Each Operating Mode (1)...................................................... Table 1-3 Pin Functions (1) ................................................................................................... 12 Table 2-1 Operating Modes ................................................................................................... 17 Table 2-2 Mode and System Control Registers..................................................................... 21 Table 3-1 Instruction Classification....................................................................................... ...
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Table 5-15 Port 7 Registers ..................................................................................................... 103 Table 5-16 Port 8 Pin Functions .............................................................................................. 104 Table 5-17 Port 8 Registers ..................................................................................................... 104 Table 5-18 Port 9 Pin Functions .............................................................................................. 114 Table 5-19 Port 9 Registers ..................................................................................................... 114 Table 6-1 Input ...
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Table 11-1 Dual-Port RAM Input and Output Pins................................................................. 227 Table 11-2 Dual-Port RAM Register Configuration ............................................................... 227 Table 12-1 System Control Register........................................................................................ 240 Table 13-1 On-Chip ROM Usage in Each MCU Mode .......................................................... 241 Table 13-2 Selection of PROM Mode ...
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Figure Figure 1-1 Block Diagram ...................................................................................................... Figure 1-2 Pin Arrangement (FP-80A, Top View) ................................................................. Figure 1-3 Pin Arrangement (CP-84, Top View) .................................................................... Figure 1-4 Pin Arrangement (CG-84, Top View) ................................................................... Figure 2-1 Address Space Map............................................................................................... 20 Figure 3-1 CPU Registers ...
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Figure 5-2 Port 2 Schematic Diagram..................................................................................... 84 Figure 5-3 Port 3 Schematic Diagram..................................................................................... 87 Figure 5-4 Port 4 Schematic Diagram (Pins P4 Figure 5-5 Port 4 Schematic Diagram (Pins P4 Figure 5-6 Port 5 Schematic Diagram (Pin P5 Figure 5-7 ...
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Figure 6-13 Input Capture Timing (1-State Delay)................................................................... 143 Figure 6-14 Input Capture Timing (1-State Delay, Buffer Mode) ............................................ 143 Figure 6-15 Buffered Input Capture with Both Edges Selected ............................................... 144 Figure 6-16 Setting of Input Capture Flag ................................................................................ 144 Figure ...
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Figure 10-1 Block Diagram of A/D Converter ......................................................................... 208 Figure 10-2 The Response of the A/D Converter ..................................................................... 214 Figure 10-3 A/D Operation in Single Mode (When Channel 1 is Selected)............................. 216 Figure 10-4 A/D Operation in Scan Mode (When ...
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Figure 17-3 Output Load Circuit .............................................................................................. 277 Figure 17-4 Basic Bus Cycle (Without Wait States) in Expanded Modes................................ 278 Figure 17-5 Basic Bus Cycle (Without 1 Wait States) in Expanded Modes............................. 279 Figure 17-6 E Clock Bus Cycle ................................................................................................ 280 ...
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The H8/330 is a single-chip microcomputer with an H8/300 CPU core and a complement of on- chip supporting modules. A variety of system functions are integrated onto the H8/330 chip. The H8/300 CPU is a high-speed Hitachi-original processor with an ...
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Block Diagram Figure 1-1 shows a block diagram of the H8/330 chip ...
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Descriptions of Blocks CPU: The CPU has a high-speed-oriented architecture in which operands are located in general registers. • Two-way general register configuration - Eight 16-bit registers Sixteen 8-bit registers • Streamlined instruction set - Instruction length: ...
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A/D Converter: A/D conversion can be performed in single or scan mode. • Eight-bit resolution • Eight input channels; selection of single mode or scan mode • Conversion can be started by an external trigger signal • Sample-and-hold I/O Ports: ...
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Clock Pulse Generator: The H8/330 can generate its system clock from a crystal oscillator, or can input an external clock signal. E-Clock Interface clock can be output for interfacing to peripheral devices. MCU Modes: The H8/330 has three ...
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Pin Assignments and Functions 1.3.1 Pin Arrangement Figure 1-2 shows the pin arrangement of the FP-80A package. Figure 1-3 shows the pin arrangement of the CP-84 package. Figure 1-4 shows the pin arrangement of the CG-84 package. RES 1 ...
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RES 12 13 XTAL 14 EXTAL NMI 18 STBY /ASCK 2 P5 /ARxD /ATxD /WE/WAIT 25 ...
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RES 12 13 XTAL 14 EXTAL NMI 18 STBY /ASCK 2 P5 /ARxD /ATxD /WE/WAIT 25 ...
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Pin Functions (1) Pin Assignments in Each Operating Mode: Table 1-2 lists the assignments of the pins of the FP-80A, CP-84, and CG-84 packages in each operating mode. The PROM mode is a non-operating mode used for programming the ...
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Table 1-2. Pin Assignments in Each Operating Mode (2) Pin No. Single-chip mode (mode 3) CP-84 FP DPRAM CG-84 -80A disabled — Ø ...
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Table 1-2. Pin Assignments in Each Operating Mode (3) Pin No. Single-chip mode (mode 3) CP-84 FP DPRAM CG-84 -80A disabled TMRI TMCI TMO 4 57 ...
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Pin Functions: Table 1-3 gives a concise description of the function of each pin. Table 1-3. Pin Functions (1) Type Symbol I/O Power Clock XTAL I EXTAL I Ø System ...
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Table 1-3. Pin Functions (2) Type Symbol I/O Data bus I Bus WAIT I control IOS O Interrupt NMI I signals IRQ IRQ 7 Operating MD ...
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Table 1-3. Pin Functions (3) Type Symbol Serial com- ATxD munication interface ARxD ASCK CTxD CRxD CSCK 16-Bit free- FTOA, running FTOB timer FTCI FTIA to FTID 8-Bit TMO , 0 timer TMO 1 TMCI , 0 TMCI 1 TMRI ...
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Table 1-3. Pin Functions (4) Type Symbol I/O Dual-port DDB I/O 7 RAM to DDB RDY O General I purpose I/O P2 ...
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Section 2. MCU Operating Modes and Address Space 2.1 Overview The H8/330 operates in three modes numbered 1, 2, and 3. An additional non-operating mode (mode 0) is used for programming the PROM version of the chip. The mode is ...
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Mode Descriptions Mode 1 (Expanded Mode without On-Chip ROM): Mode 1 supports a 64K-byte address space most of which is off-chip. In particular, the interrupt vector table is located in off-chip memory. The on-chip ROM and dual-port RAM are ...
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Address Space Map Figure 2-1 shows a memory map in each of the three operating modes. The on-chip register field consists of control, status, and data registers for the on-chip supporting modules, I/O ports, and dual-port RAM. Off-chip addresses ...
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Mode 1 (on-chip ROM disabled) H'0000 Vector table H'003D H'003E External address space H'FD7F H'FD80 On-chip RAM, 512 bytes* H'FF7F H'FF80 External address space H'FF8F H'FF90 On-chip register field H'FFA7 H'FFA8 External address space H'FFAF H'FFB0 On-chip register field H'FFFF ...
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Mode and System Control Registers (MDCR and SYSCR) Two of the control registers in the register field are the mode control register (MDCR) and system control register (SYSCR). The mode control register controls the MCU mode: the operating mode ...
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System Control Register (SYSCR) – H’FFC4 By setting or clearing the lower two bits of the system control register, software can enable or disable the on-chip RAM and dual-port RAM. The other bits in the system control register concern ...
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Coding Examples: To disable the on-chip RAM (in expanded modes): To enable the dual-port RAM (in single-chip mode): BCLR #0, @H’FFC4 BSET #1, @H’FFC4 23 ...
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Overview The H8/330 chip has the generic H8/300 CPU: an 8-bit central processing unit with a speed- oriented architecture featuring sixteen general registers. This section describes the CPU features and functions, including a concise description of the addressing modes ...
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Register Configuration Figure 3-1 shows the register structure of the CPU. There are two groups of registers: the general registers and control registers. 7 R0H R1H R2H R3H R4H R5H R6H R7H 15 3.2.1 General Registers All the general ...
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SP (R7) 3.2.2 Control Registers The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code register (CCR). (1) Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute. ...
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Bit 2—Zero (Z): This bit is set to “1” to indicate a zero result and cleared to “0” to indicate a nonzero result. Bit 1—Overflow (V): This bit is set to “1” when an arithmetic overflow occurs, and cleared to ...
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Addressing Modes The H8/330 supports eight addressing modes. Each instruction uses a subset of these addressing modes. (1) Register Direct—Rn: The register field of the instruction specifies 16-bit general register containing the operand. In most cases ...
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Immediate—#xx:8 or #xx:16: The instruction contains an 8-bit operand in its second byte 16-bit operand in its third and fourth bytes. Only MOV.W instructions can contain 16-bit immediate values. The ADDS and SUBS instructions implicitly contain the ...
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Data Formats The H8/300 CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. • Bit manipulation instructions operate on 1-bit data specified as bit ..., 7) in ...
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Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 3-3. Data type 1-Bit data 1-Bit data Byte data Byte data Word data 4-Bit BCD data 4-Bit BCD ...
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Memory Data Formats Figure 3-4 indicates the data formats in memory. Word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded as “0.” ...
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Instruction Set Table 3-1 lists the H8/330 instruction set. Table 3-1. Instruction Classification Function Data transfer Arithmetic operations Logic operations Shift Bit manipulation Branch System control Block data transfer *1 PUSH Rn is equivalent to MOV.W Rn, @–SP. POP ...
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Operation Notation Rd General register (destination) Rs General register (source) Rn, Rm General register General register field n m <EAs> Effective address: general register or memory location (EAd) Destination operand (EAs) Source operand SP Stack pointer PC ...
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Data Transfer Instructions Table 3-2 describes the data transfer instructions. Figure 3-5 shows their object code formats. Table 3-2. Data Transfer Instructions Instruction Size* Function B/W (EAs) MOV Moves data between two general registers or between a general register ...
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disp abs #imm. Op abs. Op Notation Op: Operation field d: Direction field (0–load from; 1–store to Register field disp.: ...
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Arithmetic Operations Table 3-3 describes the arithmetic instructions. See figure 3-6 in section 3.5.4, “Shift Operations” for their object codes. Table 3-3. Arithmetic Instructions Instruction Size* Function B/W Rd ± Rs ADD Performs addition or subtraction on data in ...
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Logic Operations Table 3-4 describes the four instructions that perform logic operations. See figure 3-6 in section 3.5.4, “Shift Operations” for their object codes. Table 3-4. Logic Operation Instructions Instruction Size* Function B Rd AND Performs a logical AND ...
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Notation Op: Operation field Register field #imm.: Immediate data Figure 3-6. Arithmetic, Logic, and Shift Instruction Codes ...
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Bit Manipulations Table 3-6 describes the bit-manipulation instructions. Figure 3-7 shows their object code formats. Table 3-6. Bit-Manipulation Instructions (1) Instruction Size* Function B 1 BSET Sets a specified bit in a general register or memory to “1.” The ...
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Table 3-6. Bit-Manipulation Instructions (2) Instruction Size* Function B C BIXOR XORs the C flag with the inverse of a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data. B (<bit-No.> of ...
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Before Execution of BCLR Instruction Input/output Input Input Pin state Low High DDR Pull-up Mos On Off Execution of BCLR Instruction BCLR.B #0, @P4DDR After Execution of BCLR Instruction ...
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Before Execution of BSET Instruction Input/output Input Input Pin state Low High DDR Pull-up Mos On Off Execution of BSET Instruction BSET.B #0, @PORT4 After Execution of BSET Instruction ...
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Before Execution of BSET Instruction MOV.B #80, R0L MOV.B R0L, @RAM0 MOV.B R0L, @PORT4 Input/output Input Input Pin state Low High DDR Pull-up Mos On Off RAM0 1 0 Execution of BSET ...
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Notation Op: Operation field Register field abs.: Absolute address #imm.: Immediate data ...
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Branching Instructions Table 3-7 describes the branching instructions. Figure 3-8 shows their object code formats. Table 3-7. Branching Instructions Instruction Size Function — Branches if condition cc is true. Bcc Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) ...
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Notation Op: Operation field cc: Condition field Register field disp.: Displacement abs.: Absolute address Figure 3-8. Branching Instruction Codes 8 7 disp abs. ...
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System Control Instructions Table 3-8 describes the system control instructions. Figure 3-9 shows their object code formats. Table 3-8. System Control Instructions Instruction Size Function — Returns from an exception-handling routine. RTE — Causes a transition to the power-down ...
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Op Notation Op: Operation field Register field #imm.: Immediate data Figure 3-9. System Control Instruction Codes 3.5.8 Block Data Transfer Instruction In the H8/330 the EEPMOV instruction is a block data transfer instruction. It does not ...
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Figure 3-10. Block Data Transfer Instruction/EEPROM Write Operation Code Notes on EEPMOV Instruction 1. The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified ...
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Exception Exception- handling handing request request Exception - handling state RES = 1 Reset state Notes transition to the reset state occurs when RES goes Low, except when the chip is in the hardware standby mode ...
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Power-Down State The power-down state includes three modes: the sleep mode, the software standby mode, and the hardware standby mode. (1) Sleep Mode: The sleep mode is entered when a SLEEP instruction is executed. The CPU halts, but CPU ...
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Internal address bus Internal Read signal Internal data bus (read) Internal Write signal Internal data bus (write) Figure 3-13. On-Chip Memory Access Cycle Ø Address bus AS: High RD: High WR: High Data bus: high impedance state Figure 3-14. ...
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Access to On-Chip Register Field and External Devices The on-chip register field (I/O ports, dual-port RAM, on-chip supporting module registers, etc.) and external devices are accessed in a cycle consisting of three states: T data can be accessed per ...
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Address bus AS: High RD: High WR: High Data bus: high impedance state Figure 3-16. Pin States during On-Chip Register Field Access Cycle Ø Address bus AS RD WR: High Data bus Figure 3-17 (a). External Device Access Timing ...
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T1 state Ø Address bus AS RD: High WR Data bus Figure 3-17 (b). External Device Access Timing (write) Write cycle T2 state T3 state Address Write data 57 ...
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Section 4. Exception Handling As indicated in table 4-1, the H8/330 recognizes only two kinds of exceptions: interrupts (28 sources) and the reset. There are no error or trap exceptions. When an exception occurs the CPU enters the exception-handling state ...
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Reset A reset has the highest exception-handling priority. When the RES pin goes Low, all current processing by the CPU and on-chip supporting modules halts. When RES returns from Low to High, the following hardware reset sequence is executed. ...
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RES Ø Internal address bus Internal Read signal Internal Write signal Internal data bus (16 bits) (1) Reset vector address (H'0000) (2) Starting address of reset routine (contents of H'0000–H'0001) (3) First instruction of reset routine Figure 4-1. Reset Sequence ...
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RES Ø bits) (1),(3) Reset vector address: (1)=H'0000, (3)=H'0001 (2),(4) Starting address of reset routine (contents of reset vector): (2)=upper byte, (4)=lower byte (5),(7) Starting address of ...
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Interrupts There are nine input pins for external interrupts (NMI, IRQ interrupts originating in the 16-bit free-running timer (FRT), 8-bit timers (TMR0 and TMR1), serial communication interface (SCI), and A/D converter. The features of these interrupts are: • All ...
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Table 4-2. Interrupts Priority Source High External interrupts Free-running timer 8-Bit timer 0 8-Bit timer 1 Dual-port RAM Serial communication RXI (Receive end) interface Low A/D converter Notes: 1. H’0000 and H'0001 contain the reset vector. 2. H’0002 to H’0005 ...
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Figure 4-3 shows a block diagram of the interrupt controller. Figure 4 flowchart showing the operation of the interrupt controller and the sequence by which an interrupt is accepted. This sequence is outlined below. (1) The interrupt controller ...
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NMI External (IRQ to 0 IRQ ) or internal 7 interrupt External (IRQ to 0 IRQ ) or internal 7 interrupt enable signal Figure 4-3. Block Diagram of Interrupt Controller Interrupt controller I CCR in CPU 66 NMI request Interrupt ...
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Program execution Interrupt request present NMI IRQ ? 0 Y IRQ ? 1 Y I=0 in CCR? Y Save PC Save CCR I 1, masking all interrupts except NMI To software interrupt-handling routine Figure 4-4. Hardware ...
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Interrupt accepted Interrupt priority decision. Wait for end of instruction. Interrupt request signal Ø Internal address (1) bus Internal Read signal Internal Write signal Internal 16-bit (2) data bus (1) Instruction prefetch address (Pushed on stack. Instruction is executed on ...
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Interrupt-Related Registers The interrupt controller refers to three registers in addition to the CCR. The names and attributes of these registers are listed in Table 4-3. Table 4-3. Registers Read by Interrupt Controller Name System control register IRQ sense ...
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Bits – IRQ to IRQ 0 7 the IRQ to IRQ inputs are edge-sensed or level-sensed Bit i IRQiSC Description 0 IRQi is level-sensed. 1 IRQi is sensed on the falling edge. Edge-sensed interrupt signals ...
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NMI handling routine cannot be interrupted except by another NMI. The NMI vector number is 3. Its entry is located at address H’0006 in the vector table. (2) IRQ to ...
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The interrupt controller does not reset these flag bits when accepting the interrupt. The flag bit must be reset by the software interrupt-handling routine. To reset an interrupt flag, software must read the relevant ...
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Table 4-4. Number of States before Interrupt Service No. Reason for wait 1 Interrupt priority decision 2 Wait for completion of current instruction (note 1) 3 Save PC and CCR 4 Fetch vector 5 Fetch instruction 6 Internal processing Total ...
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Figure 4-7 shows an example of damage caused when the stack pointer contains an odd address. SP-4 SP-3 SP-2 SP-1 SP(R7) Stack area Before interrupt is accepted PC : Program counter CCR : Condition code register SP : Stack pointer ...
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SP BSR instruction H'FFCF set Upper byte of program counter Lower byte of program counter General register Stack pointer Figure 4-7. Example of Damage Caused by Setting ...
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NMI and other edge-sensed interrupt request signals that arrive during the execution of an ANDC, ORC, XORC, or LDC instruction are not lost. The request is latched in the interrupt controller and detected after another instruction has been executed. LDC.B ...
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Overview The H8/330 has nine parallel I/O ports, including: • Six 8-bit input/output ports—ports and 9 • One 8-bit input port—port 7 • One 7-bit input/output port—port 8 • One 3-bit input/output port—port 5 ...
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Table 5-1 summarizes the auxiliary functions of the ports. Table 5-1. Auxiliary Functions of Input/Output Ports I/O port Expanded modes Port 1 Address bus (Low)* Port 2 ...
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Table 5-3 details the port 1 registers. Table 5-3. Port 1 Registers Name Port 1 data direction register P1DDR Port 1 data register Port 1 Data Direction Register (P1DDR)—H’FFB0 Bit 7 P1 DDR P1 7 Mode 1 Initial value 1 ...
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Mode 1: In mode 1 (expanded mode without on-chip ROM), port 1 is automatically used for address output. The port 1 data direction register is unwritable. All bits in P1DDR are automatically set to "1" and cannot be cleared to ...
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Hardware standby • 5.3 Port 2 Port 8-bit input/output port that also provides the high bits of the address bus. The function of port 2 depends on the MCU mode as indicated in Table 5-4. ...
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Pins of port 2 can drive a single TTL load and a 90pF capacitive load when they are used as output pins. They can also drive light-emitting diodes and a Darlington pair. When they are used as input pins, they ...
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MOS Pull-Ups: Are available for input pins in modes 2 and 3. Software can turn on the MOS pull-up by writing a “1” in P2DR, and turn it off by writing a “0.” The pull-ups are automatically turned off for ...
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Hardware standby P2 n 5.4 Port 3 Port 8-bit input/output port that also provides the external data bus and dual-port RAM (master-slave) data bus. The function of port 3 depends on the MCU mode as indicated in ...
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They can also drive a Darlington pair. When they are used as input pins, they have programmable MOS pull-ups. Table 5-7 details the port 3 registers. Table 5-7. Port 3 Registers Name Port 3 data direction register P3DDR Port ...
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The MOS pull-ups cannot be used in slave mode (when the dual-port RAM is enabled). P3DR should be cleared to H'00 (its initial value) in slave mode. Modes 1 and 2: In the expanded modes, port 3 is automatically used ...
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Mode Mode Figure 5-3. Port 3 Schematic Diagram DPME Mode External address write External address read WP3D: Write Port 3 DDR WP3D: Write Port 3 DDR WP3: ...
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Port 4 Port 8-bit input/output port that also provides the input and output pins for the 8-bit timers and the output pins for the PWM timers. The pin functions depend on control bits in the control ...
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Port 4 Data Register (P4DR)—H’FFB7 Bit Initial value 0 Read/Write R/W P4DR is an 8-bit register containing the data for pins P4 output pins (P4DDR = "1") it reads the value in the P4DR latch, but for ...
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P4 n WP4D: Write Port 4 DDR WP4: Write Port 4 RP4: Read Port Figure 5-4. Port 4 Schematic Diagram (Pins P4 Reset P4n DDR C WP4D Reset R Q ...
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P4 n WP4D: Write Port 4 DDR WP4: RP4 Figure 5-5. Port 4 Schematic Diagram (Pins P4 5.6 Port 5 Port 3-bit input/output port that also provides the input and output ...
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See section 9, “Serial Communication Interface” for details of the serial control bits. Pins used by the serial communication interface are switched between input and output without regard to the values in the data direction register. Pins of port 5 ...
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MOS Pull-Ups: Are available for input pins, including serial communication input pins. Software can turn the MOS pull- writing a “1” in P5DR, and turn it off by writing a “0.” Pin P5 : ...
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P5 0 WP5D: Write Port 5 DDR WP5: Write Port 5 RP5: Read Port 5 Figure 5-6. Port 5 Schematic Diagram (Pin P5 Reset DDR 0 C WP5D Reset ...
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P5 1 Figure 5-7. Port 5 Schematic Diagram (Pin P5 RP5 WP5D: Write Port 5 DDR WP5 Write Port 5 RP5: Read Port 5 95 Reset DDR 1 SCI module C WP5D Asynchronous serial receive Reset ...
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P5 2 WP5D: Write Port 5 DDR WP5 Write Port 5 RP5: Read Port 5 Figure 5-8. Port 5 Schematic Diagram (Pin P5 5.7 Port 6 Port 8-bit input/output port that also provides the input and output ...
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See section 4 “Exception Handling” and section 6, “Free-Running Timer Module” for details of the free-running timer and interrupts. Pins of port 6 can drive a single TTL load and a 90pF capacitive load when they are used as output ...
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MOS Pull-Ups: Are available for input pins, including pins used for input of timer or interrupt signals. Software can turn the MOS pull- writing a “1” in P6DR, and turn it off by writing a “0.” Pins P6 ...
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P6 n WP6D: Write Port 6 DDR WP6: Write Port 6 RP6: Read Port – 5 Figure 5-9. Port 6 Schematic Diagram (Pins P6 Reset P6n DDR C WP6D Reset R D ...
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P6 1 WP6D: Write Port 6 DDR WP6: Write Port 6 RP6: Read Port 6 Figure 5-10. Port 6 Schematic Diagram (Pin P6 Reset DDR 1 C WP6D Reset ...
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P6 6 WP6D: Write Port 6 DDR WP6: Write Port 6 RP6: Read Port 6 Figure 5-11. Port 6 Schematic Diagram (Pin P6 Reset DDR 6 C WP6D Reset ...
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P6 7 WP6D: Write Port 6 DDR WP6: RP6: Figure 5-12. Port 6 Schematic Diagram (Pin P6 5.8 Port 7 Port 8-bit input port that also provides the analog input pins for the A/D converter module. The ...
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Table 5-14. Port 7 Pin Functions (Modes Usage Pin functions I/O port P7 0 Analog input AN 0 Table 5-15. Port 7 Register Name Abbreviation Port 7 data register P7DR Port 7 Data Register (P7DR)—H’FFBE Bit 7 ...
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Port 8 Port 7-bit input/output port that also provides pins for E clock output, dual-port RAM register select input, interrupt input, and clock-synchronized serial communication. Table 5-16 lists the pin functions. Table 5-16. Port 8 Pin ...
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Port 8 Data Direction Register (P8DDR)—H’FFBD Bit 7 — P8 Modes 1 and 2 Initial value 1 Read/Write — Mode 3 Initial value 1 Read/Write — P8DDR is an 8-bit register that selects the direction of each pin in port ...
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Pin modes 1 and 2 (expanded modes), pin "1," and for general-purpose input if P8 purpose output. In mode 3 (single-chip mode), when the dual-port RAM is disabled (DPME = "0"), pin P8 used ...
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Pin P8 : This pin has the same functions in all modes. It can be used for general-purpose input or 6 output, for serial clock input or output (CSCK), or for IRQ input, P8 DDR should normally be cleared to ...
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Hardware standby P8 0 Mode WP8D: Write Port 8 DDR WP8: Write Port 8 RP8: Read Port 8 Figure 5-14. Port 8 Schematic Diagram (Pin P8 DPME Mode 3 Mode 3 108 Mode Mode ...
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P8 1 Mode WP8D: Write Port 8 DDR WP8: RP8: Figure 5-15. Port 8 Schematic Diagram (Pin P8 DPME Mode 3 Mode 3 Write Port 8 Read Port 8 109 Reset DDR 1 ...
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P8 n WP8D: Write Port 8 DDR WP8: Write Port 8 RP8: Read Port Figure 5-16. Port 8 Schematic Diagram (Pins P8 DPME Mode 3 Reset DDR n C WP8D Reset ...
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P8 4 WP8D: Write Port 8 DDR WP8: Write Port 8 RP8: Read Port 8 Figure 5-17. Port 8 Schematic Diagram (Pin P8 Reset DDR 4 C WP8D Reset ...
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P8 5 WP8D: Write Port 8 DDR WP8: Write Port 8 RP8: Read Port 8 Figure 5-18. Port 8 Schematic Diagram (Pin P8 Reset DDR 5 C WP8D Reset ...
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P8 6 WP8D: Write Port 8 DDR WP8: Write Port 8 RP8: Read Port 8 Figure 5-19. Port 8 Schematic Diagram (Pin P8 Reset DDR 6 C WP8D Reset ...
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Port 9 Port 8-bit input/output port that also provides pins for interrupt input (IRQ trigger input, system clock (Ø) output, bus control signals (in the expanded modes), and dual-port RAM interface control signals (in the single-chip ...
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Port 9 Data Direction Register (P9DDR)—H’FFC0 Bit 7 P9 DDR P9 7 Modes 1 and 2 Initial value 0 Read/Write W Mode 3 Initial value 0 Read/Write W P9DDR is an 8-bit register that selects the direction of each pin ...
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MOS pull-ups are automatically turned off. In mode 3 (single-chip mode) with the dual-port RAM disabled (DPME = "0"), these pins can be used for general-purpose input or output. In slave mode (mode 3 with DPME = "1"), these pins ...
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Software Standby Mode: All pins remain in their previous state. For RD, WR, AS, and Ø this means the High output state. Figures 5-20 to 5-25 show schematic diagrams of port WP8D: Write Port 8 DDR WP8: ...
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P9 n WP9D: Write Port 9 DDR WP9: Write Port 9 RP9: Read Port Figure 5-21. Port 9 Schematic Diagram (Pins P9 Reset DDR n C WP9D Reset ...
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Hardware standby P9 n Mode WP9D: Write Port 9 DDR WP9: Write Port 9 RP9: Read Port Figure 5-22. Port 9 Schematic Diagram (Pins P9 DPME Mode 3 Mode Mode ...
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Hardware standby Mode WP9D: Write Port 9 DDR WP9: Write Port 9 RP9: Read Port 9 * NMOS open drain if DPME="1" (Slave mode) Figure 5-23. Port 9 Schematic Diagram (Pin P9 DPME Mode ...
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Hardware standby P9 6 WP9D: Write Port 9 DDR WP9: Write Port 9 RP9: Read Port 9 * Set-priority Figure 5-24. Port 9 Schematic Diagram (Pin P9 Mode1,2 Reset DDR 6 C WP9D Reset ...
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Mode WP9D: Write Port 9 DDR WP9: Write Port 9 RP9: Read Port 9 Figure 5-25. Port 9 Schematic Diagram (Pin P9 DPME Mode 3 Reset DDR 7 C WP9D Reset ...
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Section 6. 16-Bit Free-Running Timer 6.1 Overview The H8/330 has an on-chip 16-bit free-running timer (FRT) module that uses a 16-bit free-running counter as a time base. Applications of the FRT module include rectangular-wave output (up to two independent waveforms), ...
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Internal clock sources Ø/2 External Ø/8 clock source Ø/32 FTCI Clock select Compare- match A FTOA FTOB Compare- match B Control logic Capture FTIA FTIB FTIC FTID ICIA ICIB ICIC ICID OCIA OCIB FOVI FRC: Free-Running Counter (16 bits) OCRA, ...
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Input and Output Pins Table 6-1 lists the input and output pins of the free-running timer module. Table 6-1. Input and Output Pins of Free-Running Timer Module Name Abbreviation Counter clock input FTCI Output compare A FTOA Output compare ...
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Table 6-2. Register Configuration (cont.) Name Input capture register B (High) Input capture register B (Low) Input capture register C (High) Input capture register C (Low) Input capture register D (High) Input capture register D (Low) 6.2 Register Descriptions 6.2.1 ...
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Output Compare Registers A and B (OCRA and OCRB) – H’FF94 Bit Initial value Read/ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ...
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Input capture can be buffered by using the input capture registers in pairs. When the BUFEA bit in the timer control register (TCR) is set to “1,” ICRC is used as a buffer register for ICRA as shown in Figure ...
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The input capture registers are initialized to H’0000 at a reset and in the standby modes. Note: When input capture is detected, the FRC value is transferred to the input capture register even if the input capture flag is already ...
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Bit 5 ICICE Description 0 Input capture interrupt request C (ICIC) is disabled. 1 Input capture interrupt request C (ICIC) is enabled. Bit 4 – Input Capture Interrupt D Enable (ICIDE): This bit selects whether to request input capture interrupt ...
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Bit 1 OVIE Description 0 Timer overflow interrupt request (FOVI) is disabled. 1 Timer overflow interrupt request (FOVI) is enabled. Bit 0 – Reserved: This bit cannot be modified and is always read as “1.” 6.2.5 Timer Control/Status Register (TCSR) ...
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Bit 6 – Input Capture Flag B (ICFB): This status bit is set to “1” to flag an input capture B event. If BUFEB = “0,” ICFB indicates that the FRC value has been copied to ICRB. If BUFEB = ...
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Bit 4 ICFD Description 0 To clear ICFD, the CPU must read ICFD after it has been set to "1," then write a “0” in this bit. 1 This bit is set to 1 when an FTID input signal is ...
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Bit 0 – Counter Clear A (CCLRA): This bit selects whether to clear the FRC at compare-match A (when the FRC and OCRA values match). Bit 0 CCLRA Description 0 The FRC is not cleared. 1 The FRC is cleared ...
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Bit 5 – Input Edge Select C (IEDGC): This bit causes input capture C events to be recognized on the selected edge of the input capture C signal (FTIC). In buffer mode (when BUFEA = “1”), it also causes input ...
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Bit 1 Bit 0 CKS1 CKS0 Description 0 0 Ø/2 Internal clock source 0 1 Ø/8 Internal clock source 1 0 Ø/32 Internal clock source 1 1 External clock source (rising edge) 6.2.7 Timer Output Compare Control Register (TOCR) – ...
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Bit 2 – Output Enable B (OEB): This bit enables or disables output of the output compare B signal (FTOB). When output compare B is disabled, the corresponding pin is used as a general- purpose input/output or interrupt port. Bit ...
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Register Read When the CPU reads the upper byte, the upper byte of data is sent to the CPU and the lower byte is placed in TEMP. When the CPU reads the lower byte, it receives the value in ...
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Upper byte read CPU writes data H’AA (2) Lower byte read CPU writes data H’55 Figure 6-4 (b). Read Access to FRC (When FRC Contains H’AA55) 6.4 Operation 6.4.1 FRC Incrementation Timing The FRC increments on a pulse generated ...
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Prescaler output FRC clock pulse FRC N – 1 Figure 6-5. Increment Timing for Internal Clock Source If external clock input is selected, the FRC increments on the rising edge of the FTCI clock signal. Figure 6-6 shows the ...
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Output Compare Timing (1) Setting of Output Compare Flags A and B (OCFA and OCFB): The output compare flags are set to “1” internal compare-match signal generated when the FRC value matches the OCRA or OCRB value. ...
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Output Timing: When a compare-match occurs, the logic level selected by the output level bit (OLVLA or OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Figure 6- 10 shows the timing of this operation ...
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Input at FTI pin Internal input capture signal Figure 6-12. Input Capture Timing (Usual Case) If the upper byte of ICRx is being read when the input capture signal arrives, the internal input capture signal is delayed by one ...
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Figure 6-15 shows how input capture operates when ICRA and ICRC are used in buffer mode and IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and IEDGC = 0), ...
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Timing of Input Capture Flag (ICF) Clearing: The input capture flag ICFx ( cleared when the CPU writes a “0” in this bit. Ø ICFx Figure 6-17. Clearing of Input Capture Flag 6.4.4 ...
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Interrupts The free-running timer channel can request seven types of interrupts: input capture (ICIA, ICIB, ICIC, ICID), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each interrupt is requested when the corresponding enable ...
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Application Notes Application programmers should note that the following types of contention can occur in the free- running timers. (1) Contention between FRC Write and Clear internal counter clear signal is generated during the T state of ...
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Internal address bus Internal write signal FRC clock pulse FRC Figure 6-22. FRC Write-Increment Contention (3) Contention between OCR Write and Compare-Match compare-match occurs during the T state of a write cycle to the lower byte of ...
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Internal address bus Internal write signal FRC OCRA or OCRB Compare-match signal Figure 6-23. Contention between OCR Write and Compare-Match (4) Incrementation Caused by Changing of Internal Clock Source: When an internal clock source is changed, ...
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Table 6-4. Effect of Changing Internal Clock Sources No. Description Low Low: CKS1 and CKS0 are 1 rewritten while both clock sources are Low. Low High: CKS1 and CKS0 are 2 rewritten while old clock source is Low and new ...
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Table 6-4. Effect of Changing Internal Clock Sources (cont.) No. Description High High: CKS1 and CKS0 are 4 rewritten while both clock sources are High. Timing chart Old clock source New clock source FRC clock pulse ...
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Overview The H8/330 chip includes an 8-bit timer module with two channels (TMR0 and TMR1). Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to ...
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External clock source TMCI Clock select TMO TMRI Control logic Interrupt signals TCR: Timer Control Register (8 bits) TCSR: Timer Control Status Register (8 bits) TCORA: Time Constant Register A (8 bits) TCORB: Time Constant Register B (8 bits) TCNT: ...
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Register Configuration Table 7-2 lists the registers of the 8-bit timer module. Each channel has an independent set of registers. Table 7-2. 8-Bit Timer Registers Name Timer control register Timer control/status register Timer constant register A Timer constant register ...
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Time Constant Registers A and B (TCORA and TCORB) – H’FFCA and H’FFCB (TMR0), H’FFD2 and H’FFD3 (TMR1) Bit 7 Initial value 1 Read/Write R/W TCORA and TCORB are 8-bit readable/writable registers. The timer count is continually compared with ...
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Bit 7 CMIEB Description 0 Compare-match interrupt request B (CMIB) is disabled. 1 Compare-match interrupt request B (CMIB) is enabled. Bit 6 – Compare-match Interrupt Enable A (CMIEA): This bit selects whether to request compare-match interrupt A (CMIA) when compare-match ...
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Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 7.2.4 Timer Control/Status Register (TCSR) – H’FFC9 ...
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Bit 6 CMFA Description 0 To clear CMFA, the CPU must read CMFA after it has been set to "1," then write a “0” in this bit. 1 This bit is set to 1 when TCNT = TCORA. Bit 5 ...
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Bit 1 Bit 0 OS1 OS0 Description change when compare-match A occurs Output changes to “0” when compare-match A occurs Output changes to “1” when compare-match A occurs Output inverts (toggles) ...
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External clock source TCNT clock pulse TCNT N – 1 Figure 7-3. Count Timing for External Clock Input Ø TMCI Ø TMCI Figure 7-4. Minimum External Clock Pulse Widths (Example) 7.3.2 Compare Match Timing (1) Setting of Compare-Match Flags ...
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Accordingly, when the timer count matches one of the time constants, the compare-match signal is not generated until the next period of the clock source. Figure 7-5 shows the timing of the setting of the compare-match flags. Ø f TCNT ...
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Figure 7-7 shows the timing when the output is set to toggle on compare-match A. Ø Internal compare-match A signal Timer output (TMO) (4) Timing of Compare-Match Clear: Depending on the CCLR1 and CCLR0 bits in the TCR, the timer ...
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External reset input (TMRI) Internal clear pulse TCNT 7.3.4 Setting of TCSR Overflow Flag (1) Setting of TCSR Overflow Flag (OVF): The overflow flag (OVF) is set to “1” when the timer count overflows (changes from H’FF to ...
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OVF 7.4 Interrupts Each channel in the 8-bit timer can generate three types of interrupts: compare-match A and B (CMIA and CMIB), and overflow (OVI). Each interrupt is requested when the corresponding enable bits are set in the TCR ...
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H’FF TCORA TCORB H’00 TMO pin 7.6 Application Notes Application programmers should note that the following types of contention can occur in the 8-bit timer. (1) Contention between TCNT Write and Clear internal counter clear signal is generated ...
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Contention between TCNT Write and Increment timer counter increment pulse is generated during the T state of a write cycle to the timer counter, the write takes priority and the 3 timer counter is not incremented. Figure ...
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Internal address bus Internal write signal TCNT TCORA or TCORB Compare-match signal Figure 7-15. Contention between TCOR Write and Compare-Match (4) Contention between Compare-Match A and Compare-Match B: If identical time constants are written in TCORA ...
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The pulse that increments the timer counter is generated at the falling edge of the internal clock source signal. If clock sources are changed when the old source is High and the new source is Low case No. ...
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Table 7-5. Effect of Changing Internal Clock Sources (cont.) No. Description High Low CKS1 and CKS0 are 3 rewritten while old clock source is High and new clock source is Low. High High: CKS1 and CKS0 are 4 ...
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Overview The H8/330 has an on-chip pulse-width modulation (PWM) timer module with two independent channels (PWM0 and PWM1). Both channels are functionally identical. Each PWM channel generates a rectangular output pulse with a duty factor 100%. ...
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Input and Output Pins Table 8-1 lists the output pins of the PWM timer module. There are no input pins. Table 8-1. Output Pins of PWM Timer Module Name Abbreviation PWM0 output PW0 PWM1 output PW1 8.1.4 Register Configuration ...
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The PWM timer counters can be read and written, but the write function is for test purposes only. Application software should never write to a PWM timer counter, because this may have unpredictable effects. The PWM timer counters are initialized ...
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The TCRs are 8-bit readable/writable registers that select the clock source and control the PWM outputs. The TCRs are initialized to H’ reset and in the standby modes. Bit 7 – Output Enable (OE): This bit enables the ...
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Resolution = 1/clock source frequency PWM period = PWM frequency = If the system clock frequency is 10MHz, then the resolution, period, and frequency of the PWM output for each clock source are given in Table 8-3. Table 8-3. PWM ...
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PWM Operation Figure 8 timing chart of the PWM operation. 176 ...
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Positive Logic (OS = “0”) When (OE = “0”) – (a) in Figure 8-3: The timer count is held at H’00 and PWM output is inhibited. (Pin 46 (for PW0) or pin 47 (for PW1)is used for port 4 ...
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Section 9. Serial Communication Interface 9.1 Overview The H8/330 chip includes a single-channel serial communication interface (SCI) for transferring serial data to and from other chips. Either the synchronous or asynchronous communication mode can be selected. Communication control functions are ...
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Block Diagram RDR ARxD/ RSR CRxD ATxD/ CTxD ASCK/ CSCK RSR: Receive Shift Register (8 bits) RDR: Receive Data Register (8 bits) TSR: Transmit Shift Register (8 bits) TDR: Transmit Data Register (8 bits) SMR: Serial Mode Register (8 ...
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Register Configuration Table 9-2 lists the SCI registers. Table 9-2. SCI Registers Name Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Notes: * ...
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Receive Data Register (RDR) – H’FFDD Bit 7 Initial value 0 Read/Write R The RDR stores received data. As each character is received transferred from the RSR to the RDR, enabling the RSR to receive the next ...
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The TDR is initialized to H’ reset and in the standby modes. 9.2.5 Serial Mode Register (SMR) – H’FFD8 Bit 7 C/A Initial value 0 Read/Write R/W The SMR is an 8-bit readable/writable register that controls the communication ...
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Bit 4 – Parity Mode (O asynchronous mode, when parity is enabled (PE = “1”), this bit selects even or odd parity. Even parity means that a parity bit is added to the data bits for each character ...
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Serial Control Register (SCR) – H’FFDA Bit 7 TIE Initial value 0 Read/Write R/W The SCR is an 8-bit readable/writable register that enables or disables various SCI functions initialized to H’ reset and in the ...
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Bit 4 – Receive Enable (RE): This bit enables or disables the receive function. When the receive function is enabled, the ARxD or CRxD pin is automatically used for input. When the receive function is disabled, the ARxD or CRxD ...
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Serial Status Register (SSR) – H’FFDC Bit 7 TDRE Initial value 1 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* * Software can write a “0” to clear the flags, but cannot write a “1” in these bits. The SSR is ...