HD6473308RCP10V Renesas Electronics America, HD6473308RCP10V Datasheet - Page 101

• Manufacturer Part Number: HD6473308RCP10V
• Description: MCU 5V 16K,PB-FREE 80-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/330r

Specifications of HD6473308RCP10V

• Core Size: 8-Bit
• Program Memory Size: 16KB (16K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 10MHz
• Number Of I /o: 58
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-PLCC
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 10MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 2
• Digital Ic Case: RoHS Compliant
• Controller Family/series: H8/330
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply (vcc/vdd): -
• Eeprom Size: -
• Data Converters: -
• Peripherals: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MOS pull-ups cannot be used in slave mode (when the dual-port RAM is enabled). P3DR
should be cleared to H'00 (its initial value) in slave mode.
Modes 1 and 2: In the expanded modes, port 3 is automatically used as the data bus. The values
in P3DDR and P3DR are ignored.
Mode 3: In the single-chip mode, when the dual-port RAM enable (DPME) bit in the system
control register is cleared to “0,” port 3 can be used as a general-purpose input/output port.
When DPME is set to “1,” entering the slave mode, port 3 is used as the dual-port RAM data bus
(DDB
to DDB
). P3DR should also be cleared to H'00 in slave mode.
7
0
See section 12, “Dual-Port RAM” for further information.
Reset and Hardware Standby Mode: A reset or entry to the hardware standby mode clears
P3DDR and P3DR to all “0,” and clears the DPME bit to "0." In modes 1 and 2, all pins are placed
in the data input (high-impedance) state. In mode 3 (single-chip mode), all pins are in the input
state with the MOS pull-ups off.
Software Standby Mode: In the software standby mode, P3DDR, P3DR, and the DPME bit
remain in their previous state. In modes 1 and 2 and slave mode, all pins are placed in the data
input (high-impedance) state. In mode 3 with the dual-port RAM disabled, all pins remain in their
previous input or output state.
Figure 5-3 shows a schematic diagram of port 3.
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