M30620FCAFP#U5 Renesas Electronics America, M30620FCAFP#U5 Datasheet - Page 126

• Manufacturer Part Number: M30620FCAFP#U5
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30620FCAFP#U5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: M16C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: SIM/UART
• On-chip Adc: 10-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Clock synchronous serial I/O mode
Figure 1.16.14. The transfer clock output from the multiple pins function usage
Figure 1.16.15. Serial data logic switch timing
(c) Transfer clock output from multiple pins function (UART1)
(d) Continuous receive mode
(e) Serial data logic switch function (UART2)
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B0
The multiple pins function is valid only when the internal clock is selected for UART1.
If the continuous receive mode enable bit (bits 2 and 3 at address 03B0
set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register
is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to
the transmit buffer register back again.
When the data logic select bit (bit6 at address 037D
reading from receive buffer register, data is reversed. Figure 1.16.15 shows the example of serial data
logic switch timing.
•When LSB first
Transfer clock
(no reverse)
Note: This applies when the internal clock is selected and transmission
(reverse)
Microcomputer
TxD
TxD
is performed only in clock synchronous serial I/O mode.
CLKS
2
2
CLK
T
X
“H”
“H”
“H”
D
“L”
“L”
“L”
1
1
1
(P6
(P6
(P6
7
4
5
)
)
)
D0
D0
D1
D1
D2
D2
IN
CLK
D3
D3
16
D4
D4
) = “1”, and writing to transmit buffer register or
D5
D5
D6
D6
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
IN
CLK
D7
D7
16
, bit 5 at address 037D
16
). (See Figure 1.16.14.)
M16C / 62A Group
Mitsubishi microcomputers
16
) is
123