UPD78F9222CS-CAC-A Renesas Electronics America, UPD78F9222CS-CAC-A Datasheet - Page 403

• Manufacturer Part Number: UPD78F9222CS-CAC-A
• Description: MCU 8BIT 4KB FLASH 20PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9222CS-CAC-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Option byte
Flash
memory
Function
Low-speed
internal
oscillates
Caution when
the RESET pin
is used as an
input-only port
pin (P34)
PG-FP5
programming
GUI setting
value example
Security
settings
Self
programming
function
Details of
Function
If it is selected that low-speed internal oscillator can be stopped by software,
supply of the count clock to WDT is stopped in the HALT/STOP mode,
regardless of the setting of bit 0 (LSRSTOP) of the low-speed internal oscillation
mode register (LSRCM). Similarly, clock supply is also stopped when a clock
other than the low-speed internal oscillation clock is selected as a count clock to
WDT. While the low-speed internal oscillator is operating (LSRSTOP = 0), the
clock can be supplied to the 8-bit timer H1 even in the STOP mode.
Be aware of the following when re-erasing/-writing (by on-board programming
using a dedicated flash memory programmer) an already-written device which
has been set as “The RESET pin is used as an input-only port pin (P34)” by the
option byte function.
Before supplying power to the target system, connect a dedicated flash memory
programmer and turn its power on.
If the power is supplied to the target system beforehand, the flash memory
programming mode cannot be switched to.
The above values are recommended values. Depending on the usage
environment these values may change, so set them after having performed
sufficient evaluations.
After the security setting of the batch erase is set, erasure cannot be performed
for the device. In addition, even if a write command is executed, data different
from that which has already been written to the flash memory cannot be written
because the erase command is disabled.
Self programming processing must be included in the program before
performing self programming.
No instructions can be executed while a self programming command is being
executed. Therefore, clear and restart the watchdog timer counter in advance
so that the watchdog timer does not overflow during self programming. Refer to
Table 18-10 for the time taken for the execution of self programming.
Interrupts that occur during self programming can be acknowledged after self
programming mode ends. To avoid this operation, disable interrupt servicing
(by setting MK0 and MK1 to FFH, and executing the DI instruction) before the
mode is shifted from the normal mode to the self programming mode by a
specific sequence.
RAM is not used while a self programming command is being executed.
If the supply voltage drops or the reset signal is input while the flash memory is
being written or erased, writing/erasing is not guaranteed.
The value of the blank data set during block erasure is FFH.
Set the CPU clock beforehand so that it is 1 MHz or higher during self
programming.
Execute self programming after executing the NOP and HALT instructions
immediately after executing a specific sequence to set self programming mode.
At this time, the HALT instruction is automatically released after 10 s (MAX.) +
2 CPU clocks (f
If the clock of the oscillator or an external clock is selected as the system clock,
execute the NOP and HALT instructions immediately after executing a specific
sequence to set self programming mode, wait for 8 s after releasing the HALT
status, and then execute self programming.
Check FPRERR using a 1-bit memory manipulation instruction.
The state of the pins in self programming mode is the same as that in HALT
mode.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16898EJ6V0UD
CPU
).
Cautions
p. 267
p. 267
p. 275
p. 278
p. 279
p. 282
p. 282
p. 282
p. 282
p. 282
p. 282
p. 282
p. 282
p. 282
p. 282
Page
(16/19)
401