UPD78F9222CS-CAC-A Renesas Electronics America, UPD78F9222CS-CAC-A Datasheet - Page 43

• Manufacturer Part Number: UPD78F9222CS-CAC-A
• Description: MCU 8BIT 4KB FLASH 20PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9222CS-CAC-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
Remark For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0S,
FFA9H to
FFCFH to
to FF8FH
FF99H to
Address
FFCBH
FFCCH
FFCDH
FFCEH
FFDFH
FF8DH
FF9FH
FFA0H
FFA1H
FFA2H
FFA3H
FFA4H
FFA5H
FFA6H
FFA7H
FFA8H
FFE0H
FFE1H
FF90H
FF91H
FF92H
FF93H
FF94H
FF95H
FF96H
FF97H
FF98H
ASIM6
RXB6
ASIS6
TXB6
ASIF6
CKSR6
BRGC6
ASICL6
PFCMD
PFS
FLPMC
FLCMD
FLAPL
FLAPH
FLAPHC
FLAPLC
FLW
TMC80
CR80
TM80
IF0
IF1
Symbol
and is defined as an sfr variable using the #pragma sfr directive in the CC78K0S.
<SBRF
<ADIF>
MLD67 MLD66 MLD65 MLD64 MLD63 MLD62 MLD61 MLD60
<POW
FLAP7
REG7
FLW7
<TCE
ER6>
FLAP
80>
C7
6>
7
0
0
0
0
0
0
0
0
0
<TXE6> <RXE6>
<SBRT
PRSEL
FLAP6
<TMIF
REG6
FLW6
<STIF
FLAP
010>
6>
F4
C6
6>
6
0
0
0
0
0
0
0
0
PRSEL
SBTT6
FLAP5
<TMIF
<SRIF
REG5
FLW5
FLAP
000>
C5
F3
6>
5
0
0
0
0
0
0
0
0
Table 3-3. Special Function Registers (3/4)
PRSEL
FLAP4
SBL62
<TMIF
REG4
FLW4
<SRE
PS61
FLAP
IF6>
H1>
C4
CHAPTER 3 CPU ARCHITECTURE
F2
4
0
0
0
0
0
0
0
0
Bit No.
User’s Manual U16898EJ6V0UD
PRSEL
<PIF1> <PIF0> <LVIIF>
TPS63
SBL61
FLAP3
<TMIF
REG3
FLW3
FLAP
FLAP
PS60
FLA
C11
P11
80>
F1
C3
3
0
0
0
0
0
FLCMD
PRSEL
<PIF3>
TPS62
SBL60
WEPR
FLAP2
REG2
FLW2
FLAP
FLAP
ERR
CL6
PE6
FLA
C10
TCL
P10
801
F0
C2
2
0
2
FLCMD
TXBF6
TPS61
FLAP1
<PIF2>
REG1
FLW1
FLAP
FLAP
DIR6
VCE
TCL
SL6
FE6
FLA
800
RR
P9
C9
C1
1
0
1
TXDLV
FLSPM
ISRM6
TXSF6
TPS60
FLAP0
OVE6
REG0
FLCM
FLAP
FLAP
FLW0
FPR
ERR
FLA
D0
P8
C8
C0
0
6
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
R
R
R
1
Simultaneously
Number of Bits
Manipulated
8
16
Undefined
Undefined
Undefined
Undefined
01H
FFH
00H
FFH
00H
00H
FFH
16H
00H
00H
00H
00H
00H
00H
00H
Reset
After
189
188
191
188
192
193
194
195
283
284
282
285
286
286
287
287
288
131
130
130
224
224
41