UPD78F9222CS-CAC-A Renesas Electronics America, UPD78F9222CS-CAC-A Datasheet - Page 415

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UPD78F9222CS-CAC-A

Manufacturer Part Number
UPD78F9222CS-CAC-A
Description
MCU 8BIT 4KB FLASH 20PIN
Manufacturer
Renesas Electronics America
Series
78K0S/Kx1+r
Datasheet

Specifications of UPD78F9222CS-CAC-A

Core Processor
78K0S
Core Size
8-Bit
Speed
10MHz
Connectivity
LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
4th edition
Edition
Modification of Caution in 11.3 (6) Asynchronous serial interface control register 6
(ASICL6)
Modification of Caution 1 in Figure 11-10 Format of Asynchronous Serial Interface
Control Register 6 (ASICL6)
Modification of Caution in 11.4.2 (1) Registers used
Addition of Caution 2 to 16.3 (2) Low-voltage detection level select register (LVIS)
Addition of 17.3 Caution When the RESET Pin Is Used as an Input-Only Port Pin
(P34)
Addition of description to 18.6.1 X1 and X2 pins
Addition of Remark 1 to 18.8 Flash Memory Programming by Self Writing
Modification of description of internal verify 1 in and addition of description and Remark of
internal verify 2 to Table 18-11 Self Programming Controlling Commands
Partial modification of and addition to 18.8.2 Cautions on self programming function
Addition of Cautions 2, 3 and 5 to and modification of Caution 4 in Figure 18-12 Format
of Flash Programming Mode Control Register (FLPMC)
Modification of Caution in and addition of description on FPRERR to 18.8.3 (2) Flash
protect command register (PFCMD)
Addition of Caution to 18.8.3 (3) Flash status register (PFS)
Modification of description and Note of internal verify 1 in and addition of description of
internal verify 2 to Figure 18-15 Format of Flash Programming Command Register
(FLCMD)
Modification of Caution in Figure 18-16 Format of Flash Address Pointer H/L
(FLAPH/FLAPL) and Caution 1 in Figure 18-17 Format of Flash Address Pointer H/L
Compare Registers (FLAPHC/FLAPLC)
Addition of description to 18.8.4 Example of shifting normal mode to self
programming mode and 18.8.5 Example of shifting self programming mode to
normal mode
Addition of description of internal verify 1 and 2 to 18.8.9 Example of internal verify
operation in self programming mode
Addition of description to 18.8.10 Examples of operation when command execution
time should be minimized in self programming mode and 18.8.11 Examples of
operation when interrupt-disabled time should be minimized in self programming
mode
• Modification of MAX. values of low-level input voltage (V
• Modification of conditions of high-level output voltage
• Modification of MAX. values of supply current (I
• Addition of CPU Clock Frequency, Peripheral Clock Frequency
• Modification of Caution in A/D Converter Characteristics
• Addition of formula to calculate power consumption of internal pull-up resistor
• Modification of MAX. values of low-level input voltage (V
• Modification of conditions of high-level output voltage
• Addition of CPU Clock Frequency, Peripheral Clock Frequency
• Modification of Caution in A/D Converter Characteristics
current, low-level input leakage current, high-level output leakage current and low-level
output leakage current
APPENDIX E REVISION HISTORY
User’s Manual U16898EJ6V0UD
Description
DD5
) in STOP mode
IL3
IL2
), high-level input leakage
)
CHAPTER 11 SERIAL
INTERFACE UART6
CHAPTER 16 LOW-
VOLTAGE DETECTOR
CHAPTER 17 OPTION
BYTE
CHAPTER 18 FLASH
MEMORY
CHAPTER 21
ELECTRICAL
SPECIFICATIONS
(TARGET VALUES)
((A2) grade product)
CHAPTER 20
ELECTRICAL
SPECIFICATIONS
(Standard product, (A)
grade product)
Applied to:
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