UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 814

• Manufacturer Part Number: UPD70F3735GC-GAD-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GC-GAD-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
CB1STR
CB1TIC
CB1TX
CB1TXL
CB2CTL0
CB2CTL1
CB2CTL2
CB2RIC
CB2RX
CB2RXL
CB2STR
CB2TIC
CB2TX
CB2TXL
CCLS
CKC
CLM
CRCD
CRCIN
CTBP
CTPC
CTPSW
DA0CS0
DA0M
DADC0
DADC1
DADC2
DADC3
DBC0
DBC1
DBC2
DBC3
DBPC
DBPSW
DCHC0
DCHC1
DCHC2
DCHC3
DDA0H
DDA0L
DDA1H
DDA1L
DDA2H
DDA2L
DDA3H
Symbol
CSIB1 status register
Interrupt control register
CSIB1 transmit data register
CSIB1 transmit data register L
CSIB2 control register 0
CSIB2 control register 1
CSIB2 control register 2
Interrupt control register
CSIB2 receive data register
CSIB2 receive data register L
CSIB2 status register
Interrupt control register
CSIB2 transmit data register
CSIB2 transmit data register L
CPU operation clock status register
Clock control register
Clock monitor mode register
CRC data register
CRC input register
CALLT base pointer
CALLT execution status saving register
CALLT execution status saving register
D/A conversion value setting register 0
D/A converter mode register
DMA addressing control register 0
DMA addressing control register 1
DMA addressing control register 2
DMA addressing control register 3
DMA transfer count register 0
DMA transfer count register 1
DMA transfer count register 2
DMA transfer count register 3
Exception/debug trap status saving register
Exception/debug trap status saving register
DMA channel control register 0
DMA channel control register 1
DMA channel control register 2
DMA channel control register 3
DMA destination address register 0H
DMA destination address register 0L
DMA destination address register 1H
DMA destination address register 1L
DMA destination address register 2H
DMA destination address register 2L
DMA destination address register 3H
Name
APPENDIX B REGISTER INDEX
CSI
INTC
CSI
CSI
CSI
CSI
CSI
INTC
CSI
CSI
CSI
INTC
CSI
CSI
CG
CG
CLM
CRC
CRC
CPU
CPU
CPU
DAC
DAC
DMAC
DMAC
DMAC
DMAC
DMAC
DMAC
DMAC
DMAC
CPU
CPU
DMAC
DMAC
DMAC
DMAC
DMAC
DMAC
DMAC
DMAC
DMAC
DMAC
DMAC
Unit
Page 798 of 816
474
630
467
467
468
471
472
630
467
467
474
630
467
467
165
168
694
704
704
31
30
30
427
426
596
596
596
596
595
595
595
595
31
31
597
597
597
597
594
594
594
594
594
594
594
Page
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