UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 331

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Therefore, the transfer destination’s maximum receivable baud rate (BRmax) is as follows.
Similarly, the maximum allowable transfer rate (FLmax) can be obtained as follows.
Therefore, the transfer destination’s minimum receivable baud rate (BRmin) is as follows.
The allowable baud rate error of UARTn and the transfer destination can be obtained as follows from the
expressions described above for computing the minimum and maximum baud rate values.
Remarks 1. The reception precision depends on the number of bits in one frame, the base clock frequency,
2. k: BRGCn setting value
and the division ratio (k). The higher the base clock frequency and the larger the division ratio
(k), the higher the precision.
8
20
50
100
255
Table 13-4. Maximum and Minimum Allowable Baud Rate Error
Division Ratio (k)
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE n (UARTn)
10
11
×
BRmax
BRmin
FLmax
FLmax
=
User’s Manual U15905EJ2V1UD
=
=
Maximum Allowable
(FLmax/11)
=
11
(FLmin/11)
Baud Rate Error
21
×
20
+3.53%
+4.26%
+4.56%
+4.66%
+4.72%
k
FL
−
k
−
2
FL
−
−
k
2
1
1
+
×
=
=
×
2
k
11
21
21
×
20k
22k
k
k
FL
−
+
2
2
=
Minimum Allowable
Brate
Brate
Baud Rate Error
21
2
k
×
–3.61%
–4.31%
–4.58%
–4.67%
–4.73%
−
k
2
FL
329