UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 361

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note TRC is cleared and the SDA line becomes high impedance when bit 5 (WREL) of the IIC control register
Remark
(IICC) is set and the wait state is released at ninth clock when bit 3 (TRC) of the IIC status register (IICS)
= 1.
Condition for clearing (TRC = 0)
• When a stop condition is detected
• Cleared by LREL = 1
• When IICE changes from 1 to 0
• Cleared by WREL = 1
• When ALD changes from 0 to 1
• After reset
Master
• When “1” is output to the first byte’s LSB (transfer
Slave
• When a start condition is detected
When not used for communication
Condition for clearing (COI = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL = 1
• When IICE changes from 1 to 0
• After reset
TRC
COI
direction specification bit)
WREL: Bit 5 of IIC control register (IICC)
LREL:
IICE:
0
1
0
1
Receive status (other than transmit status). The SDA line is set to high impedance.
Transmit status. The value in the SO latch is enabled for output to the SDA line (valid starting
at the falling edge of the first byte’s ninth clock).
Addresses do not match.
Addresses match.
Bit 6 of IIC control register (IICC)
Bit 7 of IIC control register (IICC)
Note
User’s Manual U15905EJ2V1UD
CHAPTER 15 I
Detection of transmit/receive status
Detection of matching addresses
Condition for setting (TRC = 1)
Master
• When a start condition is generated
Slave
• When “1” is input by the first byte’s LSB (transfer
Condition for setting (COI = 1)
• When the received address matches the local
direction specification bit)
address (SVA) (set at the rising edge of the
eighth clock).
2
C BUS
(2/3)
359