UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 354

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

352
(6) Serial clock counter
(7) Interrupt request signal generator
(8) Serial clock controller
(9) Serial clock wait controller
(10) ACK output circuit, stop condition detector, start condition detector, and ACK detector
(11) Data hold time correction circuit
This counter counts the serial clocks that are output and the serial clocks that are input during transmit/receive
operations and is used to verify that 8-bit data was sent or received.
This circuit controls the generation of interrupt request signals (INTIIC).
An I
• Eighth or ninth clock of the serial clock (set by WTIM bit
• Interrupt request generated when a stop condition is detected (set by SPIE bit
Note WTIM bit: Bit 3 of IIC control register (IICC)
In master mode, this circuit generates the clock output via the SCL pin from a sampling clock.
This circuit controls the wait timing.
These circuits are used to output and detect various control signals.
This circuit generates the hold time for data corresponding to the falling edge of the serial clock.
2
C interrupt is generated following either of two triggers.
SPIE bit: Bit 4 of IIC control register (IICC)
User’s Manual U15905EJ2V1UD
CHAPTER 15 I
2
C BUS
Note
)
Note
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