UPD70F3743GJ-GAE-AX Renesas Electronics America, UPD70F3743GJ-GAE-AX Datasheet - Page 447

• Manufacturer Part Number: UPD70F3743GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3743GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 128
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JJ3
Remark
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
Other than above Setting prohibited
ADA0FR0 Bits
ADA0FR3 to
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
Conversion time:
Stabilization time:
Trigger response time: If a software trigger, external trigger, or timer trigger is generated after the stabilization
In the high-speed conversion mode, the conversion is started after the stabilization time elapsed from the
ADA0M0.ADA0CE bit is set to 1, and A/D conversion is performed only during the conversion time (2.6 to 10.4
μ
ends.
In continuous conversion mode, the stabilization time is inserted only before the first conversion, and not
inserted after the second conversion (the A/D converter remains running).
Cautions 1. Set as 2.6
s). The A/D conversion end interrupt request signal (INTAD) is generated immediately after the conversion
Table 13-3. Conversion Time Selection in High-Speed Conversion Mode (ADA0HS1 Bit = 1)
26/f
52/f
78/f
104/f
130/f
156/f
182/f
208/f
234/f
260/f
286/f
312f
(+ Stabilization Time)
XX
XX
XX
Conversion Time
XX
XX
XX
XX
XX
XX
XX
XX
XX
(+13/f
(+26/f
(+39/f
2. In the high-speed conversion mode, rewriting of the ADA0M0, ADA0M2, ADA0S, ADA0PFM,
(+50/f
(+50/f
(+50/f
(+50/f
(+50/f
(+50/f
(+50/f
(+50/f
(+50/f
and ADA0PFT registers and trigger input are prohibited during the stabilization time.
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
)
)
)
)
)
)
)
)
)
)
)
)
Actual A/D conversion time (2.6 to 10.4
A/D converter setup time (1
time, it is inserted before the conversion time.
μ
s ≤ conversion time ≤ 10.4
Setting prohibited Setting prohibited Setting prohibited 6.5
Setting prohibited 2.6
Setting prohibited 3.9
3.25
(+1.5625
4.0625
(+1.5625
4.875
(+1.5625
5.6875
(+1.5625
6.5
(+1.5625
7.3125
(+1.5625
8.125
(+1.5625
8.9375
(+1.5625
9.75
(+1.5625
f
XX
μ
μ
s
μ
= 32 MHz
s
μ
μ
s
μ
s
μ
μ
s
μ
s
s
s
s
μ
μ
μ
μ
μ
μ
μ
μ
μ
s)
s)
s)
s)
s)
s)
s)
s)
s)
(+1.3
(+1.95
5.2
(+2.5
6.5
(+2.55
7.8
(+2.5
9.1
(+2.5
10.4
(+2.5
Setting prohibited Setting prohibited Setting prohibited
Setting prohibited Setting prohibited Setting prohibited
Setting prohibited Setting prohibited Setting prohibited
Setting prohibited Setting prohibited Setting prohibited
A/D Conversion Time
f
XX
μ
μ
μ
μ
μ
μ
s
s
s
s
s
s
μ
μ
μ
μ
μ
μ
= 20 MHz
μ
s
s)
μ
s)
μ
s)
s)
s)
s or longer)
s)
s)
μ
s.
μ
3.25
(+1.625
4.875
(+2.4375
6.5
(+3.125
8.125
(+3.125
9.75
(+3.125
Setting prohibited Setting prohibited
Setting prohibited Setting prohibited
s)
f
XX
μ
μ
s
μ
= 16 MHz
s
μ
μ
s
s
s
μ
μ
μ
μ
s)
μ
s)
s)
s)
CHAPTER 13 A/D CONVERTER
s)
(+3.25
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
f
μ
XX
s
= 4 MHz
μ
s)
Page 431 of 892
Response
Trigger
Time
3/f
3/f
3/f
3/f
3/f
3/f
3/f
3/f
3/f
3/f
3/f
3/f
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX