UPD70F3743GJ-GAE-AX Renesas Electronics America, UPD70F3743GJ-GAE-AX Datasheet - Page 880

• Manufacturer Part Number: UPD70F3743GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3743GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 128
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JJ3
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
16-bit
timer/
event
counter Q
(TMQ)
Function
TQ0CTL1.TQ0EEE
bit
TQ0IOC2
register
TQ0OPT0
register
TQ0CCR0
register
TQ0CCR1
register
TQ0CCR2
register
TQ0CCR3
register
TQ0CNT
register
External event
count mode
External trigger
pulse output
mode,
one-shot pulse
output mode,
pulse width
measurement
mode
Details of
Function
The TQ0ETS1 and TQ0ETS0 bits are valid only when the external trigger pulse
output mode (TQ0CTL1.TQ0MD2 to TQ0CTL1.TQ0MD0 bits = 010) or the one-
shot pulse output mode (TQ0CTL1.TQ0MD2 to TQ0CTL1.TQ0MD0 = 011) is set.
Rewrite the TQ0CCS3 to TQ0CCS0 bits when the TQ0CTL0.TQ0CE bit = 0. (The
same value can be written when the TQ0CE bit = 1.) If rewriting was mistakenly
performed, clear the TQ0CE bit to 0 and then set the bits again.
Be sure to clear bits 1 to 3 to “0”.
Accessing the TQ0CCR0 register is prohibited in the following statuses. For
details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
• When the CPU operates with the internal oscillation clock
Accessing the TQ0CCR1 register is prohibited in the following statuses. For
details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
• When the CPU operates with the internal oscillation clock
Accessing the TQ0CCR2 register is prohibited in the following statuses. For
details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
• When the CPU operates with the internal oscillation clock
Accessing the TQ0CCR3 register is prohibited in the following statuses. For
details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
• When the CPU operates with the internal oscillation clock
Accessing the TQ0CNT register is prohibited in the following statuses. For details,
see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
• When the CPU operates with the internal oscillation clock
To use the external event count mode, specify that the valid edge of the TIQ00
pin capture trigger input is not detected (by clearing the TQ0IOC1.TQ0IS1 and
TQ0IOC1.TQ0IS0 bits to “00”).
When using the external trigger pulse output mode, one-shot pulse output mode,
and pulse width measurement mode, select the internal clock as the count clock
(by clearing the TQ0CTL1.TQ0EEE bit to 0).
This bit can be set to 1 only when the interrupt request signals (INTTQ0CC0 and
INTTQ0CCk) are masked by the interrupt mask flags (TQ0CCMK0 to
TQ0CCMKk) and the timer output (TOQ0k) is performed at the same time.
However, the TQ0CCR0 and TQ0CCRk registers must be set to the same value
(see 8.5.1 (2) (d) Operation of TQ0CCR1 to TQ0CCR3 registers).
stopped
stopped
stopped
stopped
stopped
Cautions
APPENDIX E LIST OF CAUTIONS
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