UPD70F3743GJ-GAE-AX Renesas Electronics America, UPD70F3743GJ-GAE-AX Datasheet - Page 875

• Manufacturer Part Number: UPD70F3743GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3743GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 128
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JJ3
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
Port
functions
Bus
control
functions
Function
PFn.PFnm bit
in port mode
Cautions on bit
manipulation
instruction for
port n register
(Pn)
Cautions on on-
chip debug pins
Cautions on
P05/INTP2/
DRST pin
Cautions on
P53 pin when
power is turned
on
Hysteresis
characteristics
Pin status when
internal ROM
EXIMC register
BSC register
DWC0 register
Details of
Function
In port mode, the PFn.PFnm bit is valid only in the output mode (PMn.PMnm bit =
0). In the input mode (PMnm bit = 1), the value of the PFnm bit is not reflected in
the buffer.
When a 1-bit manipulation instruction is executed on a port that provides both
input and output functions, the value of the output latch of an input port that is not
subject to manipulation may be written in addition to the targeted bit.
Therefore, it is recommended to rewrite the output latch when switching a port
from input mode to output mode.
The following action must be taken if on-chip debugging is not used.
• Clear the OCDM0 bit of the OCDM register (special register) (0)
At this time, fix the P05/INTP2/DRST pin to low level from when reset by the
RESET pin is released until the above action is taken.
If a high level is input to the DRST pin before the above action is taken, it may
cause a malfunction (CPU deadlock).
Handle the P05 pin with the utmost care.
After reset by the WDT2RES signal, clock monitor (CLM), or low-voltage detector
(LVI), the P05/INTP2/DRST pin is not initialized to function as an on-chip debug
pin (DRST). The OCDM register holds the current value.
The P05/INTP2/DRST pin has an internal pull-down resistor (30 kΩ TYP.). After a
reset by the RESET pin, a pulldown resistor is connected. The pull-down resistor
is disconnected when the OCDM0 bit is cleared (0).
When the power is turned on, the following pin may output an undefined level
temporarily, even during reset.
• P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO pin
In port mode, the following port pins do not have hysteresis characteristics.
When a write access is performed to the internal ROM area, address, data, and
control signals are activated in the same way as access to the external memory
area.
Set the EXIMC register from the internal ROM or internal RAM area before
making an external access.
After setting the EXIMC register, be sure to insert a NOP instruction.
Write to the BSC register after reset, and then do not change the set values. Also,
do not access an external memory area until the initial settings of the BSC
register are complete.
Be sure to set bits 14, 12, 10, and 8 to “1”, and clear bits 15, 13, 11, 9, 7, 5, 3,
and 1 to “0”.
The internal ROM and internal RAM areas are not subject to programmable wait,
and are always accessed without a wait state. The on-chip peripheral I/O area is
also not subject to programmable wait, and only wait control from each peripheral
function is performed.
P00 to P06
P31 to P35, P38, P39
P40 to P42
P50 to P55
P66, P68 to P610, P612, P613
P80
P90 to P97, P99, P910, P912 to P915
Cautions
APPENDIX E LIST OF CAUTIONS
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