UPD70F3744GJ-GAE-AX Renesas Electronics America, UPD70F3744GJ-GAE-AX Datasheet - Page 737

• Manufacturer Part Number: UPD70F3744GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3744GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 128
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JJ3
23.3 Register
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
The clock monitor is controlled by the clock monitor mode register (CLM).
(1) Clock monitor mode register (CLM)
The CLM register is a special register. This can be written only in a special combination of sequences (see 3.4.7
Special registers).
This register is used to set the operation mode of the clock monitor.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Cautions 1. Once the CLME bit has been set to 1, it cannot be cleared to 0 by any means other
CLM
After reset: 00H
2. When a reset by the clock monitor occurs, the CLME bit is cleared to 0 and the
CLME
7
0
0
1
than reset.
RESF.CLMRF bit is set to 1.
Disable clock monitor operation.
Enable clock monitor operation.
R/W
6
0
Address: FFFFF870H
5
0
Clock monitor operation enable or disable
4
0
3
0
2
0
CHAPTER 23 CLOCK MONITOR
1
0
CLME
<0>
Page 721 of 892