SAB-C167SR-LM HA+ Infineon Technologies, SAB-C167SR-LM HA+ Datasheet - Page 81

• Manufacturer Part Number: SAB-C167SR-LM HA+
• Description: IC MCU 16BIT MQFP-144
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAB-C167SR-LM HA+

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144- BSQFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: 1xUSART, 1xSSC
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 9
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 16 Channel
• Packages: PG-MQFP-144
• Max Clock Frequency: 25.0 MHz
• Sram (incl. Cache): 4.0 KByte
• A / D Input Lines (incl. Fadc): 16
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: B167SRLMHAZNP; B167SRLMHAZXP; SABC167SRLMHAX; SP000103456

Bus Cycle Control via READY Input
The duration of an external bus cycle can be controlled by the external circuitry via the
READY input signal.
Synchronous READY permits the shortest possible bus cycle but requires the input
signal to be synchronous to the reference signal CLKOUT.
Asynchronous READY puts no timing constraints on the input signal but incurs one
waitstate minimum due to the additional synchronization stage.
Table 20
Parameter
Input setup time to CLKOUT rising edge
Valid for: READY input
Input hold time after CLKOUT rising edge
Valid for: READY input
Asynchronous READY input low time
Notes (Valid also for
4. Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
5. READY sampled HIGH at this sampling point generates a READY controlled
6. These timings are given for test purposes only, in order to assure recognition at a
7. Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an
8. If the next following bus cycle is READY controlled, an active READY signal must be
Data Sheet
waitstate, READY sampled LOW at this sampling point terminates the currently
running bus cycle.
specific clock edge. If the Asynchronous READY signal does not fulfill the indicated
setup and hold times with respect to CLKOUT, it must fulfill
synchronized. Proper deactivation of READY is guaranteed if READY is deactivated
in response to the trailing (rising) edge of the corresponding command (RD or WR).
additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC
waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC
waitstate this delay is zero.
disabled before the first valid sample point for the next bus cycle. This sample point
depends on the MTTC waitstate of the current cycle, and on the MCTC waitstates
and the ALE mode of the next following cycle. If the current cycle uses a multiplexed
bus the intrinsic MUX waitstate adds another CLKOUT cycle to the READY
deactivation time.
READY Timing (Operating Conditions apply)
Figure
20)
6)
79
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Symbol
25
26
27
CC
CC
CC
Min.
12
0
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5
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Electrical Parameters
27
Limits
25
in order to be safely
Max.
–
–
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V3.3, 2005-02
C167CR
C167SR
Unit
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ns
ns