SAF-TC1130-L150EB-G BB Infineon Technologies, SAF-TC1130-L150EB-G BB Datasheet - Page 48

• Manufacturer Part Number: SAF-TC1130-L150EB-G BB
• Description: IC MCU 32BIT TRICOR 16KB LBGA208
• Manufacturer: Infineon Technologies
• Series: TC11xxr

Specifications of SAF-TC1130-L150EB-G BB

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Type: ROMless
• Ram Size: 144K x 8
• Voltage - Supply (vcc/vdd): 1.43 V ~ 1.58 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LSBGA
• Data Bus Width: 32 bit
• Program Memory Size: 32 KB
• Data Ram Size: 144 KB
• Interface Type: 3xASC, 2xSSC, I2C, 2xMLI, Ethernet 10, 100 Mbits, s, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 9
• Operating Supply Voltage: 1.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Packages: PG-LBGA-208
• Max Clock Frequency: 150.0 MHz
• Sram (incl. Cache): 144.0 KByte
• Can Nodes: 4
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: FT1130L150EBGBBXP; SAF-TC1130-L150EB-GBB; SAF-TC1130-L150EB-GBBINTR; SAF-TC1130-L150EB-GBBTR; SAF-TC1130-L150EB-GBBTR; SAFTC1130L150EBBBXT; SP000106119; SP000106538; SP000743584

Figure 3-6
Data Sheet
Decoder
Address
Interrupt
Control
Control
Decoder
Address
Control
Interrupt
Clock
to DMA
Control
Enable
Clock
M/S Select
to DMA
1)
General Block Diagram of the SSC Interfaces
EIR
TIR
RIR
f
f
f
f
1)
EIR
TIR
RIR
SSC0
SSC1
CLC0
CLC1
SSC0
Module
(Kernel)
SSC1
Module
(Kernel)
Master
Master
Master
Master
Master
Master
Slave
Slave
Slave
Slave
Slave
Slave
SLSO0
M/S Select
Enable
SLSO0
SLSO[2:1]
SLSO[4:3]
SLSO[7:5]
SLSO[2:1]
SLSO[4:3]
SLSO[7:5]
SLSI[7:2]
SLSI[7:2]
MRSTA
MRSTB
MTSR
MTSRA
MTSRB
MRST
SCLKA
SCLKB
SLCK
SLSI1
SLSI1
1)
MRSTA
MRSTB
MTSR
MTSRA
MTSRB
MRST
SCLKA
SCLKB
SLCK
These lines are not connected
42
1)
1)
1)
1)
Control
Control
Control
Control
Control
Control
Port 2
Port 1
Port 0
Port 3
Port 1
Port 2
Functional Description
P2.2/MRST0
P2.3/MTSR0
P2.4/SCLK0
P2.12/SLSO03
P2.14/SLSO04
P1.15/SLSI0
P1.11/SLSO01
P1.13/SLSO02
P0.6/SLSO00
P0.4/SLSI1
P0.7/SLSO10
P3.7/SLSO05
P3.9/SLSO06
P3.11/SLSO07
P3.8/SLSO15
P3.10/SLSO16
P3.12/SLSO17
P1.12/SLSO11
P1.14/SLSO12
P2.13/SLSO13
P2.15/SLSO14
P2.5/MRST1A
P3.13/MRST1B
P2.6/MTSR1A
P3.14/MTSR1B
P2.7SCLK1A
P3.15/SCLK1B
MCB04486_mod
V1.1, 2008-12
TC1130