AT89S8252-24PI Atmel, AT89S8252-24PI Datasheet - Page 18

• Manufacturer Part Number: AT89S8252-24PI
• Description: MCU W/SPI 8KB FLSH 2K EEP 40-DIP
• Manufacturer: Atmel
• Series: 89Sr

Specifications of AT89S8252-24PI

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: AT89S825224PI

UART
Serial Peripheral
Interface
Figure 7. SPI Master-slave Interconnection
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AT89S8252
CLOCK GENERATOR
SPI
MSB
8-BIT SHIFT REGISTER
The UART in the AT89S8252 operates the same way as the UART in the AT89C51 and
AT89C52. For further information on the UART operation, refer to the Atmel web site
(http://www.atmel.com). From the home page, select “Products”, then “Microcontrollers,
then “8051-Architecture”. Click on “Documentation”, then on “Other Documents”. Open
the document “AT89 Series Hardware Description”.
The serial peripheral interface (SPI) allows high-speed synchronous data transfer
between the AT89S8252 and peripheral devices or between several AT89S8252
devices. The AT89S8252 SPI features include the following:
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The interconnection between master and slave CPUs with SPI is shown in the following
figure. The SCK pin is the clock output in the master mode but is the clock input in the
slave mode. Writing to the SPI data register of the master CPU starts the SPI clock gen-
erator, and the data written shifts out of the MOSI pin and into the MOSI pin of the slave
CPU. After shifting one byte, the SPI clock generator stops, setting the end of transmis-
sion flag (SPIF). If both the SPI interrupt enable bit (SPIE) and the serial port interrupt
enable bit (ES) are set, an interrupt is requested.
The Slave Select input, SS/P1.4, is set low to select an individual SPI device as a slave.
When SS/P1.4 is set high, the SPI port is deactivated and the MOSI/P1.5 pin can be
used as an input.
There are four combinations of SCK phase and polarity with respect to serial data,
which are determined by control bits CPHA and CPOL. The SPI data transfer formats
are shown in Figure 8 and Figure 9.
Full-Duplex, 3-Wire Synchronous Data Transfer
Master or Slave Operation
1.5 MHz Bit Frequency (max.)
LSB First or MSB First Data Transfer
Four Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wakeup from Idle Mode (Slave Mode Only)
MASTER
LSB
MISO
MOSI MOSI
SCK
SS
V
CC
MISO
SCK
SS
MSB
8-BIT SHIFT REGISTER
SLAVE
LSB
0401G–MICRO–3/06