AT89S8252-24PI Atmel, AT89S8252-24PI Datasheet - Page 8

• Manufacturer Part Number: AT89S8252-24PI
• Description: MCU W/SPI 8KB FLSH 2K EEP 40-DIP
• Manufacturer: Atmel
• Series: 89Sr

Specifications of AT89S8252-24PI

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: AT89S825224PI

Watchdog and Memory Control Register The WMCON register contains control bits for the Watchdog Timer (shown in
Table 3). The EEMEN and EEMWE bits are used to select the 2K bytes on-chip EEPROM, and to enable byte-write. The
DPS bit selects one of two DPTR registers available.
Table 3. WMCON—Watchdog and Memory Control Register
8
WMCON Address = 96H
Bit
Symbol
PS2
PS1
PS0
EEMWE
EEMEN
DPS
WDTRST
RDY/BSY
WDTEN
AT89S8252
PS2
7
Function
Prescaler Bits for the Watchdog Timer. When all three bits are set to “0”, the watchdog timer has a nominal period of
16 ms. When all three bits are set to “1”, the nominal period is 2048 ms.
EEPROM Data Memory Write Enable Bit. Set this bit to “1” before initiating byte write to on-chip EEPROM with the
MOVX instruction. User software should set this bit to “0” after EEPROM write is completed.
Internal EEPROM Access Enable. When EEMEN = 1, the MOVX instruction with DPTR will access on-chip EEPROM
instead of external data memory. When EEMEN = 0, MOVX with DPTR accesses external data memory.
Data Pointer Register Select. DPS = 0 selects the first bank of Data Pointer Register, DP0, and DPS = 1 selects the
second bank, DP1
Watchdog Timer Reset and EEPROM Ready/Busy Flag. Each time this bit is set to “1” by user software, a pulse is
generated to reset the watchdog timer. The WDTRST bit is then automatically reset to “0” in the next instruction cycle.
The WDTRST bit is Write-Only. This bit also serves as the RDY/BSY flag in a Read-Only mode during EEPROM write.
RDY/BSY = 1 means that the EEPROM is ready to be programmed. While programming operations are being executed,
the RDY/BSY bit equals “0” and is automatically reset to “1” when programming is completed.
Watchdog Timer Enable Bit. WDTEN = 1 enables the watchdog timer and WDTEN = 0 disables the watchdog timer.
PS1
6
PS0
5
EEMWE
4
EEMEN
3
DPS
2
Reset Value = 0000 0010B
WDTRST
1
WDTEN
0401G–MICRO–3/06
0