ATMEGA88-20PU Atmel, ATMEGA88-20PU Datasheet - Page 284

IC AVR MCU 8K 20MHZ 5V 28DIP

ATMEGA88-20PU

Manufacturer Part Number
ATMEGA88-20PU
Description
IC AVR MCU 8K 20MHZ 5V 28DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA88-20PU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
SPI/TWI/USART
Total Internal Ram Size
1KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
6-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
28
Package Type
PDIP
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRTS2080A, ATASTK512-EK1-IND
Minimum Operating Temperature
- 40 C
Package
28PDIP
Family Name
ATmega
Maximum Speed
20 MHz
For Use With
ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
27. Memory Programming
27.1
284
Program And Data Memory Lock Bits
ATmega48/88/168
The ATmega88/168 provides six Lock bits which can be left unprogrammed (“1”) or can be pro-
grammed (“0”) to obtain the additional features listed in
erased to “1” with the Chip Erase command.The ATmega48 has no separate Boot Loader sec-
tion. The SPM instruction is enabled for the whole Flash if the SELFPRGEN fuse is programmed
(“0”), otherwise it is disabled.
Table 27-1.
Notes:
Table 27-2.
Notes:
BLB12
BLB11
BLB02
BLB01
LB2
LB1
LB Mode
Lock Bit Byte
1
2
3
(2)
(2)
(2)
(2)
1. “1” means unprogrammed, “0” means programmed
2. Only on ATmega88/168.
1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.
2. “1” means unprogrammed, “0” means programmed
Memory Lock Bits
Lock Bit Byte
Lock Bit Protection Modes
LB2
1
1
0
(1)
LB1
1
0
0
Bit No
7
6
5
4
3
2
1
0
Protection Type
No memory lock features enabled.
Further programming of the Flash and EEPROM is disabled in
Parallel and Serial Programming mode. The Fuse bits are
locked in both Serial and Parallel Programming mode.
Further programming and verification of the Flash and EEPROM
is disabled in Parallel and Serial Programming mode. The Boot
Lock bits and Fuse bits are locked in both Serial and Parallel
Programming mode.
(1)(2)
Description
Boot Lock bit
Boot Lock bit
Boot Lock bit
Boot Lock bit
Lock bit
Lock bit
(1)
Table
27-2. The Lock bits can only be
Default Value
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
2545S–AVR–07/10
(1)

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