LPC2114FBD64,151 NXP Semiconductors, LPC2114FBD64,151 Datasheet - Page 16

• Manufacturer Part Number: LPC2114FBD64,151
• Description: IC ARM7 MCU FLASH 128K 64-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2100r

Specifications of LPC2114FBD64,151

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: MCB2100 - BOARD EVAL NXP LPC211X/LPC212X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 568-1222; 935274514151; LPC2114FBD64-S

NXP Semiconductors
LPC2114_2124_6
Product data sheet
6.10.1 Features
6.11.1 Features
6.11.2 Features available in LPC2114/2124/01 only
6.11 SPI serial I/O controller
the capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
The I
I
The LPC2114/2124 each contain two SPIs. The SPI is a full duplex serial interface,
designed to be able to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends a byte of data to the slave, and
the slave always sends a byte of data to the master.
2
C-bus).
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Standard I
Easy to configure as Master, Slave, or Master/Slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
Compliant with Serial Peripheral Interface (SPI) specification.
Synchronous, Serial, Full Duplex communication.
Combined SPI master and slave.
Maximum data bit rate of
Eight to 16 bits per frame.
When the SPI interface is used in Master mode, the SSELn pin is not needed (can be
used for a different function).
2
C-bus implemented in LPC2114/2124 supports a bit rate up to 400 kbit/s (Fast
2
C-bus may be used for test and diagnostic purposes.
2
C-bus compliant interface.
Rev. 06 — 10 December 2007
1
8
of the input clock rate.
Single-chip 16/32-bit microcontrollers
2
C-bus is a multi-master bus; it can be
LPC2114/2124
© NXP B.V. 2007. All rights reserved.
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