LPC2212FBD144,551 NXP Semiconductors, LPC2212FBD144,551 Datasheet - Page 18

• Manufacturer Part Number: LPC2212FBD144,551
• Description: IC ARM7 MCU FLASH 128K 144-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2200r

Specifications of LPC2212FBD144,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: OM10091 - KIT DEV PHYCORE-ARM7/LPC2220568-1757 - BOARD EVAL FOR LPC220X ARM MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 568-1228; 935275686551; LPC2212FBD144-S

NXP Semiconductors
LPC2212_2214_4
Product data sheet
6.11.1 Features
6.12.1 Features
6.12.2 Features available in LPC2212/2214/01 only
6.11 I
6.12 SPI serial I/O controller
The I
line (SCL), and a serial data line (SDA). Each device is recognized by a unique address
and can operate as either a receiver-only device (e.g. an LCD driver or a transmitter with
the capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
The I
I
The LPC2212/2214 each contain two SPIs. The SPI is a full duplex serial interface,
designed to be able to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends a byte of data to the slave, and
the slave always sends a byte of data to the master.
2
2
C-bus).
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C-bus serial I/O controller
Standard I
Easy to configure as Master, Slave, or Master/Slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
Compliant with Serial Peripheral Interface (SPI) specification.
Synchronous, Serial, Full Duplex communication.
Combined SPI master and slave.
Maximum data bit rate of
Eight to 16 bits per frame.
2
2
C-bus is a bidirectional bus for inter-IC control using only two wires: a serial clock
C-bus implemented in LPC2212/2214 supports a bit rate up to 400 kbit/s (Fast
2
C-bus may be used for test and diagnostic purposes.
2
C-bus compliant interface.
Rev. 04 — 3 January 2008
1
8
of the input clock rate.
2
C-bus is a multi-master bus; it can be
16/32-bit ARM microcontrollers
LPC2212/2214
© NXP B.V. 2008. All rights reserved.
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