LPC2212FBD144,551 NXP Semiconductors, LPC2212FBD144,551 Datasheet - Page 38

• Manufacturer Part Number: LPC2212FBD144,551
• Description: IC ARM7 MCU FLASH 128K 144-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2200r

Specifications of LPC2212FBD144,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: OM10091 - KIT DEV PHYCORE-ARM7/LPC2220568-1757 - BOARD EVAL FOR LPC220X ARM MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 568-1228; 935275686551; LPC2212FBD144-S

NXP Semiconductors
Table 10.
C
[1]
[2]
[3]
[4]
[5]
Table 11.
[1]
LPC2212_2214_4
Product data sheet
Symbol
t
t
t
t
t
t
t
Access cycle
standard read
standard write
burst read - initial
burst read - subsequent 3
BLSHDNV
CHDV
CHWEL
CHBLSL
CHWEH
CHBLSH
CHDNV
L
= 25 pF; T
Except on initial access, in which case the address is set up T
T
Latest of address valid, CS LOW, OE LOW to data valid.
Address valid to data valid.
Earliest of CS HIGH, OE HIGH, address change to data invalid.
See the LPC2114/2124/2212/2214 User Manual for a description of the WSTn bits.
cy(CCLK)
External memory interface dynamic characteristics
Parameter
BLS HIGH to data invalid
time
XCLK HIGH to data valid
time
XCLK HIGH to WE LOW
time
XCLK HIGH to BLS LOW
time
XCLK HIGH to WE HIGH
time
XCLK HIGH to BLS HIGH
time
XCLK HIGH to data invalid
time
Standard read access specifications
=
amb
1
CCLK.
= 40 C.
Max frequency
f
f
f
f
MAX
MAX
MAX
MAX
--------------------------------
t
--------------------------------- -
t
------------------------------- -
t
-------------------------------- -
t
RAM
WRITE
INIT
ROM
2
2
1
Conditions
+
+
+
WST 1
WST 1
+
+
WST 2
+
1
20 ns
20 ns
+
20 ns
5 ns
Rev. 04 — 3 January 2008
WST 1
WST
WST
integer
N/A
WST 1
WST 2
cy(CCLK)
[2]
[1]
0; round up to
setting
Min
(2
-
-
-
-
-
-
t
------------------------------- - 2
t
-------------------------------- 2
t
------------------------------------------- -
INIT
RAM
WRITE
t
t
cy CCLK
earlier.
cy CCLK
…continued
T
t
cy CCLK
+
cy(CCLK)
+
20 ns
20 ns
–
t
CYC
–
)
–
+
5
5
Memory access time requirement
t
t
t
t
INIT
RAM
WRITE
ROM
16/32-bit ARM microcontrollers
LPC2212/2214
t
t
t
cy CCLK
cy CCLK
cy CCLK
Typ Max
-
-
-
-
-
-
-
t
cy CCLK
(2
10
10
10
10
10
10
–
T
20 ns
© NXP B.V. 2008. All rights reserved.
2
2
cy(CCLK)
+
+
1
WST 1
WST 1
+
WST 2
) + 5 ns
–
–
20 ns
38 of 45
20 ns
–
Unit
ns
ns
ns
ns
ns
ns
5 ns