ST7FLITE39F2U6 STMicroelectronics, ST7FLITE39F2U6 Datasheet - Page 108

• Manufacturer Part Number: ST7FLITE39F2U6
• Description: IC MCU 8BIT 8K FLASH 20QFN
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE39F2U6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-QFN
• For Use With: 497-8406 - BOARD STF20NM50FD/STF7LITE39BF2497-8403 - BOARD DEMO STCC08 AC SW DETECTOR497-6398 - BOARD EVAL ST7FLITE39/STM1403497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5514 - EVAL BOARD THERMO CONTROL REFRIG497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5635

ST7LITE3xF2
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
11.5.9.3 LIN Reception
In LIN mode the reception of a byte is the same as
in SCI mode but the LINSCI has features for han-
dling the LIN Header automatically (identifier de-
tection) or semiautomatically (Synch Break detec-
tion) depending on the LIN Header detection
mode. The detection mode is selected by the
LHDM bit in the SCICR3.
Additionally, an automatic resynchronization fea-
ture can be activated to compensate for any clock
deviation, for more details please refer to
11.5.9.5 LIN Baud
LIN Header Handling by a Slave
Depending on the LIN Header detection method
the LINSCI will signal the detection of a LIN Head-
er after the LIN Synch Break or after the Identifier
has been successfully received.
Note:
It is recommended to combine the Header detec-
tion function with Mute mode. Putting the LINSCI
in Mute mode allows the detection of Headers only
and prevents the reception of any other charac-
ters.
This mode can be used to wait for the next Header
without being interrupted by the data bytes of the
current message in case this message is not rele-
vant for the application.
Synch Break Detection (LHDM = 0):
When a LIN Synch Break is received:
– The RDRF bit in the SCISR register is set. It in-
– The LHDF flag in the SCICR3 register indicates
– An interrupt is generated if the LHIE bit in the
– Then the LIN Synch Field is received and meas-
108/173
dicates that the content of the shift register is
transferred to the SCIDR register, a value of
0x00 is expected for a Break.
that a LIN Synch Break Field has been detected.
SCICR3 register is set and the I[1:0] bits are
cleared in the CCR register.
ured.
– If automatic resynchronization is enabled (LA-
– If automatic resynchronization is disabled (LA-
SE bit = 1), the LIN Synch Field is not trans-
ferred to the shift register: There is no need to
clear the RDRF bit.
SE bit = 0), the LIN Synch Field is received as
a normal character and transferred to the
SCIDR register and RDRF is set.
Rate.
Section
Note:
In LIN slave mode, the FE bit detects all frame er-
ror which does not correspond to a break.
Identifier Detection (LHDM = 1):
This case is the same as the previous one except
that the LHDF and the RDRF flags are set only af-
ter the entire header has been received (this is
true whether automatic resynchronization is ena-
bled or not). This indicates that the LIN Identifier is
available in the SCIDR register.
Notes:
During LIN Synch Field measurement, the SCI
state machine is switched off: No characters are
transferred to the data register.
LIN Slave parity
In LIN Slave mode (LINE and LSLV bits are set)
LIN parity checking can be enabled by setting the
PCE bit.
In this case, the parity bits of the LIN Identifier
Field are checked. The identifier character is rec-
ognized as the third received character after a
break character (included):
The bits involved are the two MSB positions (7th
and 8th bits if M = 0; 8th and 9th bits if M = 0) of
the identifier character. The check is performed as
specified by the LIN specification:
start bit
LIN Synch
Break
ID0
identifier bits
P0
P1
ID1 ID2 ID3 ID4 ID5 P0 P1
=
=
ID0
ID1
Identifier Field
LIN Synch
Field
⊕
⊕
ID1
ID3
⊕
⊕
parity bits
parity bits
ID2
ID4
⊕
⊕
Identifier
Field
ID4
ID5
stop bit
M = 0