ST7FMC2R7T6TR STMicroelectronics, ST7FMC2R7T6TR Datasheet - Page 128

• Manufacturer Part Number: ST7FMC2R7T6TR
• Description: IC MCU 8BIT 32K FLASH 64-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FMC2R7T6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: 497-8402 - BOARD EVAL COMPLETE INVERTER497-8400 - KIT IGBT PWR MODULE CTRL ST7MC497-6408 - BOARD EVAL BLDC SENSORLESS MOTOR497-4734 - EVAL KIT 3KW POWER DRIVER BOARD497-4733 - EVAL KIT 1KW POWER DRIVER BOARD497-4732 - EVAL KIT 300W POWER DRIVER BOARD497-4731 - EVAL KIT PWR DRIVER CONTROL BRD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ST7MC1xx/ST7MC2xx
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
10.5.9.5 LIN Baud Rate
Baud rate programming is done by writing a value
in the LPR prescaler or performing an automatic
resynchronization as described below.
Automatic Resynchronization
To automatically adjust the baud rate based on
measurement of the LIN Synch Field:
– Write the nominal LIN Prescaler value (usually
– Set the LASE bit to enable the Auto Synchroni-
When Auto Synchronization is enabled, after each
LIN Synch Break, the time duration between five
falling edges on RDI is sampled on f
result of this measurement is stored in an internal
15-bit register called SM (not user accessible)
(See
sociated LPFR and LPR registers) are automati-
cally updated at the end of the fifth falling edge.
During LIN Synch field measurement, the SCI
state machine is stopped and no data is trans-
ferred to the data register.
10.5.9.6 LIN Slave Baud Rate Generation
In LIN mode, transmission and reception are driv-
en by the LIN baud rate generator
Note: LIN Master mode uses the Extended or
Conventional prescaler register to generate the
baud rate.
If LINE bit = 1 and LSLV bit = 1 then the Conven-
tional and Extended Baud Rate Generators are
disabled: the baud rate for the receiver and trans-
128/309
1
depending on the nominal baud rate) in the
LPFR / LPR registers.
zation Unit.
Figure
68). Then the LDIV value (and its as-
CPU
and the
mitter are both set to the same value, depending
on the LIN Slave baud rate generator:
with:
LDIV is an unsigned fixed point number. The man-
tissa is coded on 8 bits in the LPR register and the
fraction is coded on 4 bits in the LPFR register.
If LASE bit = 1 then LDIV is automatically updated
at the end of each LIN Synch Field.
Three registers are used internally to manage the
auto-update of the LIN divider (LDIV):
- LDIV_NOM (nominal value written by software at
LPR/LPFR addresses)
- LDIV_MEAS (results of the Field Synch meas-
urement)
- LDIV (used to generate the local baud rate)
The control and interactions of these registers is
explained in
on the LDUM bit setting (LIN Divider Update Meth-
od)
Note:
As explained in
can be updated by two concurrent actions: a
transfer from LDIV_MEAS at the end of the LIN
Sync Field and a transfer from LDIV_NOM due
to a software write of LPR. If both operations
occur at the same time, the transfer from
LDIV_NOM has priority.
Tx = Rx =
Figure 69
Figure 69
(16
and
f
CPU
*
LDIV)
Figure
and
Figure
70. It depends
70, LDIV