IC MCU 4MHZ 8K OTP 44-PLCC

MC68HC705C8ACFN

Manufacturer Part NumberMC68HC705C8ACFN
DescriptionIC MCU 4MHZ 8K OTP 44-PLCC
ManufacturerFreescale Semiconductor
SeriesHC05
MC68HC705C8ACFN datasheet
 


Specifications of MC68HC705C8ACFN

Core ProcessorHC05Core Size8-Bit
Speed2.1MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o24
Program Memory Size8KB (8K x 8)Program Memory TypeOTP
Ram Size304 x 8Voltage - Supply (vcc/vdd)3 V ~ 5.5 V
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case44-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Eeprom Size-Data Converters-
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Freescale Semiconductor, Inc.
MC68HC705C8A
MC68HSC705C8A
Technical Data
M68HC05
Microcontrollers
MC68HC705C8A/D
Rev. 3, 3/2002
WWW.MOTOROLA.COM/SEMICONDUCTORS
For More Information On This Product,
Go to: www.freescale.com

MC68HC705C8ACFN Summary of contents

  • Page 1

    ... Freescale Semiconductor, Inc. M68HC05 Microcontrollers WWW.MOTOROLA.COM/SEMICONDUCTORS For More Information On This Product, Go to: www.freescale.com MC68HC705C8A MC68HSC705C8A Technical Data MC68HC705C8A/D Rev. 3, 3/2002 ...

  • Page 2

    ... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...

  • Page 3

    ... Freescale Semiconductor, Inc. MC68HC705C8A MC68HSC705C8A Technical Data To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.motorola.com/semiconductors/ The following revision history table summarizes changes contained in this document ...

  • Page 4

    ... Freescale Semiconductor, Inc. Technical Data Revision Date Level 1.7 Pin Functions (V PP May, 2001 2.1 Removed note following PD5–PD0) 14.2 Introduction 14.7 44-Pin Quad Flat Pack (QFP) March, 2002 3 drawing from Case #824E to Case #824A Revision History Description — Added description of programming voltage ) pin 1 ...

  • Page 5

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705C8A Section 1. General Description . . . . . . . . . . . . . . . . . . . . 21 Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Section 3. Central Processor Unit (CPU Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Section 6. Low-Power Modes Section 7. Parallel Input/Output (I/O Section 8. Capture/Compare Timer . . . . . . . . . . . . . . . . . 89 Section 9. EPROM/OTPROM (PROM 103 Section 10. Serial Communications Interface (SCI 121 Section 11 ...

  • Page 6

    ... Freescale Semiconductor, Inc. List of Sections Technical Data 6 List of Sections For More Information On This Product, Go to: www.freescale.com MC68HC705C8A — Rev. 3 MOTOROLA ...

  • Page 7

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705C8A 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.7.1 1.7.2 1.7.3 1.7.4 1.7.5 1.7.6 1.7.7 1.7.8 1.7.9 1.7.10 1.7.11 2.1 2.2 2.3 2.4 MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, Section 1. General Description Contents ...

  • Page 8

    ... Freescale Semiconductor, Inc. Table of Contents 2.5 2.6 2.7 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.4 5.1 5.2 Technical Data 8 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 EPROM/OTPROM (PROM Bootloader ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Section 3. Central Processor Unit (CPU) Contents ...

  • Page 9

    ... Freescale Semiconductor, Inc. 5.3 5.3.1 5.3.2 5.3.3 5.3.4 6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.4 6.4.1 6.4.2 6.5 7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.4 7.4.1 7.4.2 7.4.3 MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Power-On Reset (POR External Reset ...

  • Page 10

    ... Freescale Semiconductor, Inc. Table of Contents 7.5 7.5.1 7.5.2 7.5.3 7.6 8.1 8.2 8.3 8.3.1 8.3.2 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 9.1 9.2 9.3 9.3.1 9.3.2 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 Technical Data 10 Port Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Data Direction Register Port C Logic ...

  • Page 11

    ... Freescale Semiconductor, Inc. 9.4.7 9.4.8 9.5 9.5.1 9.5.2 9.5.3 9.6 Section 10. Serial Communications Interface (SCI) 10.1 10.2 10.3 10.4 10.5 10.5.1 10.5.2 10.6 10.6.1 10.6.2 10.6.3 10.6.4 10.6.5 11.1 11.2 11.3 11.4 11.4.1 11.4.2 11.5 MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, Execute Program in RAM ...

  • Page 12

    ... Freescale Semiconductor, Inc. Table of Contents 11.6 11.7 11.7.1 11.7.2 11.7.3 11.8 11.9 11.9.1 11.9.2 11.9.3 12.1 12.2 12.3 12.3.1 12.3.2 12.3.3 12.3.4 12.3.5 12.3.6 12.3.7 12.3.8 12.4 12.4.1 12.4.2 12.4.3 12.4.4 12.4.5 12.5 12.6 Technical Data 12 Serial Clock Polarity and Phase . . . . . . . . . . . . . . . . . . . . . . .146 SPI Error Conditions ...

  • Page 13

    ... Freescale Semiconductor, Inc. 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 13.10 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 13.11 5.0-Volt Serial Peripheral Interface (SPI) Timing . . . . . . . . . . 185 13.12 3.3-Volt Serial Peripheral Interface (SPI) Timing . . . . . . . . . . 187 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 MC68HC705C8A — ...

  • Page 14

    ... Freescale Semiconductor, Inc. Table of Contents 15.1 15.2 15.3 A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 Technical Data 14 Section 15. Ordering Information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Appendix A. MC68HSC705C8A Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 5.0-Volt High-Speed DC Electrical Characteristics .202 3 ...

  • Page 15

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705C8A Figure 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 2-1 2-2 3-1 3-2 3-3 3-4 3-5 3-6 4-1 4-2 4-3 4-4 4-5 MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, Title Option Register (Option) ...

  • Page 16

    ... Freescale Semiconductor, Inc. List of Figures Figure 5-1 5-2 5-3 5-4 6-1 6-2 6-3 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-10 8-9 8-11 8-12 9-1 9-2 Technical Data 16 Title Programmable COP Watchdog Diagram . . . . . . . . . . . . . . .63 Programmable COP Reset Register (COPRST) ...

  • Page 17

    ... Freescale Semiconductor, Inc. Figure 9-3 9-4 9-5 9-6 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, Title Program Register (PROG) ...

  • Page 18

    ... Freescale Semiconductor, Inc. List of Figures Figure 14-1 14-2 14-3 14-4 14-5 14-6 Technical Data 18 Title MC68HC705C8AP Package Dimensions (Case #711 192 MC68HC705C8AS Package Dimensions (Case #734A .193 MC68HC705C8AFN Package Dimensions (Case #777 194 MC68HC705C8AFS Package Dimensions (Case #777B .195 MC68HC705C8AFB Package Dimensions (Case #824A) ...

  • Page 19

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705C8A Table 2-1 4-1 5-1 7-1 7-2 7-3 9-1 9-2 10-1 10-2 10-3 11-1 12-1 12-2 12-3 12-4 12-5 12-6 12-7 15-1 MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, Title Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Reset/Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . . . 57 Programmable COP Timeout Period Selection ...

  • Page 20

    ... Freescale Semiconductor, Inc. List of Tables Table A-1 A-2 Technical Data 20 Title Programmable COP Timeout Period Selection . . . . . . . . . . . 202 MC68HSC705C8A Order Numbers . . . . . . . . . . . . . . . . . . . . 209 List of Tables For More Information On This Product, Go to: www.freescale.com Page MC68HC705C8A — Rev. 3 MOTOROLA ...

  • Page 21

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705C8A 1.1 Contents 1.2 1.3 1.4 1.5 1.6 1.7 1.7.1 1.7.2 1.7.3 1.7.3.1 1.7.3.2 1.7.3.3 1.7.4 1.7.5 1.7.6 1.7.7 1.7.8 1.7.9 1.7.10 1.7.11 MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, Section 1. General Description Introduction ...

  • Page 22

    ... Freescale Semiconductor, Inc. General Description 1.2 Introduction The MC68HC705C8A, an enhanced version of the MC68HC705C8 member of the low-cost, high-performance M68HC05 Family of 8-bit microcontroller units (MCU). The MC68HSC705C8A, introduced in Appendix A. the MC68HC705C8A. The M68HC05 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs ...

  • Page 23

    ... Freescale Semiconductor, Inc. • • NOTE: A line over a signal name indicates an active low signal. For example, RESET is active high and RESET is active low. Any reference to voltage, current, or frequency specified in this document will refer to the nominal values. The exact values and their tolerance or limits are specified in Section 13 ...

  • Page 24

    ... Freescale Semiconductor, Inc. General Description RAM0 — Random-Access Memory Control Bit 0 RAM1 — Random-Access Memory Control Bit 1 SEC — Security Bit This bit is implemented as an erasable, programmable read-only memory (EPROM) cell and is not affected by reset. IRQ — Interrupt Request Pin Sensitivity Bit IRQ is set only by reset, but can be cleared by software ...

  • Page 25

    ... Freescale Semiconductor, Inc. EPROM PROGRAMMING V CONTROL PP EPROM/OTPROM — 7744 BYTES (144 BYTES CONFIGURABLE) BOOT ROM — 240 BYTES RESET CPU CONTROL IRQ CPU REGISTERS 0 0 CONDITION CODE REGISTER OSC2 OSCILLATOR OSC1 COP WATCHDOG AND CLOCK MONITOR V DD POWER Port B pins also function as external interrupts. ...

  • Page 26

    ... Freescale Semiconductor, Inc. General Description 1.6 Pin Assignments The MC68HC705C8A is available in six packages: • • • • • • The pin assignments for these packages are shown in Figure Technical Data 26 40-pin plastic dual in-line package (PDIP) 40-pin ceramic dual in-line package (cerdip) ...

  • Page 27

    ... Freescale Semiconductor, Inc. MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, PA5 7 PA4 8 9 PA3 PA2 10 PA1 11 PA0 12 13 PB0 14 PB1 PB2 15 PB3 16 17 PB4 Figure 1-4. 44-Lead PLCC/CLCC Pin Assignments PD7 34 TCAP 35 OSC2 36 OSC1 RESET 41 IRQ PA7 Figure 1-5. 44-Pin QFP Pin Assignments General Description Go to: www ...

  • Page 28

    ... Freescale Semiconductor, Inc. General Description Technical Data 28 1 RESET 2 IRQ PA7 4 PA6 5 PA5 6 PA4 7 PA3 8 PA2 9 PA1 10 PA0 11 PB0 12 PB1 13 PB2 14 PB3 PB4 17 PB5 18 PB6 19 20 PB7 Figure 1-6. 42-Pin SDIP Pin Assignments General Description For More Information On This Product, Go to: www.freescale.com ...

  • Page 29

    ... Freescale Semiconductor, Inc. 1.7 Pin Functions This subsection describes the MC68HC705C8A signals. Reference is made, where applicable, to other sections that contain more detail about the function being performed. 1.7.1 V and and V DD from a single power supply. Very fast signal transitions occur on the MCU pins, placing high short-duration current demands on the power supply ...

  • Page 30

    ... Freescale Semiconductor, Inc. General Description 1.7.3 OSC1 and OSC2 The OSC1 and OSC2 pins are the control connections for the 2-pin on-chip oscillator. The oscillator can be driven by: • • • NOTE: The frequency of the internal oscillator is f internal oscillator output by two to produce the internal clock with a frequency ...

  • Page 31

    ... Freescale Semiconductor, Inc. 1.7.3.2 Ceramic Resonator To reduce cost, use a ceramic resonator instead of a crystal. Use the circuit shown in ceramic resonator or the circuit shown in Figure 1-10 resonator, and follow the resonator manufacturer’s recommendations. The external component values required for maximum stability and reliable starting depend upon the resonator parameters ...

  • Page 32

    ... Freescale Semiconductor, Inc. General Description 1.7.3.3 External Clock Signal An external clock from another CMOS-compatible device can drive the OSC1 input, with the OSC2 pin unconnected, as NOTE: The bus frequency (f the processor clock cycle is two times the f 1.7.4 External Reset Pin (RESET) A logic 0 on the bidirectional RESET pin forces the MCU to a known startup state ...

  • Page 33

    ... Freescale Semiconductor, Inc. 1.7.7 Output Compare Pin (TCMP) The TCMP pin is the output compare pin for the on-chip capture/compare timer. See 1.7.8 Port A I/O Pins (PA7–PA0) These eight I/O lines comprise port A, a general-purpose, bidirectional I/O port. The pins are programmable as either inputs or outputs under software control of the data direction registers. See 1.7.9 Port B I/O Pins (PB7– ...

  • Page 34

    ... Freescale Semiconductor, Inc. General Description Technical Data 34 General Description For More Information On This Product, Go to: www.freescale.com MC68HC705C8A — Rev. 3 MOTOROLA ...

  • Page 35

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705C8A 2.1 Contents 2.2 2.3 2.4 2.5 2.6 2.7 2.2 Introduction This section describes the organization of the on-chip memory. 2.3 Memory Map The central processor unit (CPU) can address eight Kbytes of memory and input/output (I/O) registers. The program counter typically advances one address at a time through memory, reading the program instructions and data ...

  • Page 36

    ... Freescale Semiconductor, Inc. Memory subroutine call to save the CPU state. The stack pointer decrements during pushes and increments during pulls. Figure 2-1 shown in registers. Additional I/O registers have these addresses: • • • 2.4 Input/Output (I/O) The first 32 addresses of memory space, from $0000 to $001F, are the I/O section ...

  • Page 37

    ... Freescale Semiconductor, Inc. 2.6 EPROM/OTPROM (PROM) An MCU with a quartz window has a maximum of 7744 bytes of EPROM. The quartz window allows the EPROM erasure with ultraviolet light MCU without a quartz window, the EPROM cannot be erased and serves a maximum 7744 bytes of OTPROM (see Section 9. EPROM/OTPROM 2.7 Bootloader ROM The 240 bytes at addresses $1F00– ...

  • Page 38

    ... Freescale Semiconductor, Inc. Memory $0000 I/O REGISTERS 32 BYTES $001F $0020 UNUSED 16 BYTES $002F $0030 RAM 32 BYTES (1) $004F RAM0 = 1 $0050 $00BF RAM 176 BYTES $00C0 $00FF $0100 USER PROM 96 BYTES (1) $015F RAM1 = 0 $0160 USER PROM 7584 BYTES $1EFF $1F00 BOOTLOADER ROM 240 BYTES ...

  • Page 39

    ... Freescale Semiconductor, Inc. Addr. Register Name Read: Port A Data Register $0000 (PORTA) See page 78. Reset: Read: Port B Data Register $0001 (PORTB) See page 81. Reset: Read: Port C Data Register $0002 (PORTC) See page 85. Reset: Read: Port D Fixed Input Register $0003 (PORTD) See page 88. ...

  • Page 40

    ... Freescale Semiconductor, Inc. Memory Addr. Register Name SPI Control Register $000A (SPCR) See page 149. SPI Status Register $000B (SPSR) See page 151. SPI Data Register $000C (SPDR) See page 149. Baud Rate Register $000D (Baud) See page 136. SCI Control Register 1 ...

  • Page 41

    ... Freescale Semiconductor, Inc. Addr. Register Name Read: Timer Status Register $0013 (TSR) See page 96. Reset: Read: Bit 15 Input Capture Register $0014 High (ICRH) See page 100. Reset: Read: Input Capture Register $0015 Low (ICRL) See page 100. Reset: Read: Output Compare Register ...

  • Page 42

    ... Freescale Semiconductor, Inc. Memory Addr. Register Name EPROM Programming $001C Register (PROG) See page 109. Programmable COP Reset $001D Register (COPRST) See page 64. Programmable COP Control $001E Register (COPCR) See page 64. $001F Unimplemented Option Register $1FDF (Option) See page 116. * Implemented as an EPROM cell ...

  • Page 43

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705C8A Section 3. Central Processor Unit (CPU) 3.1 Contents 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.4 3.2 Introduction This section describes the central processor unit (CPU) registers. MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, Introduction ...

  • Page 44

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 3.3 CPU Registers Figure 3-1 within the CPU and are not part of the memory map. Bit Bit 12 11 Technical Data 44 shows the five CPU registers. These are hard-wired registers Bit Bit Bit HALF-CARRY FLAG ...

  • Page 45

    ... Freescale Semiconductor, Inc. 3.3.1 Accumulator The accumulator (A) shown in register. The CPU uses the accumulator to hold operands and results of arithmetic and non-arithmetic operations. Read: Write: Reset: 3.3.2 Index Register In the indexed addressing modes, the CPU uses the byte in the index register (X) shown in the operand ...

  • Page 46

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 3.3.3 Stack Pointer The stack pointer (SP) shown in contains the address of the next free location on the stack. During a reset or after the reset stack pointer (RSP) instruction, the stack pointer initializes to $00FF. The address in the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack ...

  • Page 47

    ... Freescale Semiconductor, Inc. 3.3.5 Condition Code Register The condition code register (CCR) shown in register whose three most significant bits are permanently fixed at 111. The condition code register contains the interrupt mask and four bits that indicate the results of prior instructions. Read: ...

  • Page 48

    ... Freescale Semiconductor, Inc. Central Processor Unit (CPU) N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logical operation, or data manipulation produces a negative result (bit 7 in the results is a logic 1). Reset has no effect on the negative flag. Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logical operation, or data manipulation produces a result of $00 ...

  • Page 49

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705C8A 4.1 Contents 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.4 4.2 Introduction This section describes how interrupts temporarily change the normal processing sequence. MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, Section 4. Interrupts Introduction ...

  • Page 50

    ... Freescale Semiconductor, Inc. Interrupts 4.3 Interrupt Sources These sources can generate interrupts: • • • • • The IRQ pin, port B pins, SCI, and SPI can be masked (disabled) by setting the I bit of the condition code register (CCR). The software interrupt (SWI) instruction is non-maskable. ...

  • Page 51

    ... Freescale Semiconductor, Inc. 4.3.2 External Interrupt (IRQ) An interrupt signal on the IRQ pin latches an external interrupt request. After completing the current instruction, the CPU tests these bits: • • Setting the I bit in the CCR disables external interrupts. If the IRQ latch is set and the I bit is clear, the CPU then begins the interrupt sequence ...

  • Page 52

    ... Freescale Semiconductor, Inc. Interrupts EDGE- AND LEVEL-SENSITIVE TRIGGER V DD INTERRUPT PIN Figure 4-1. External Interrupt Internal Function Diagram IRQ PIN a. Edge-Sensitive Trigger Condition. The minimum pulse width (t or 250 MHz). The period t OP execute the interrupt service routine plus 19 t IRQ 1 ...

  • Page 53

    ... Freescale Semiconductor, Inc. 4.3.3 Port B Interrupts When these three conditions are true, a port B pin (PBx) acts as an external interrupt pin: • • • MOR1 is an erasable, programmable read-only memory (EPROM) register that enables the port B pullup device. Data from MOR1 is latched on the rising edge of the voltage on the RESET pin. See ...

  • Page 54

    ... Freescale Semiconductor, Inc. Interrupts READ $0005 WRITE $0005 RESET WRITE $0001 READ $0001 IRQ FROM OPTION REGISTER FROM OTHER PORT B PINS IRQ RESET EXTERNAL INTERRUPT VECTOR FETCH Technical Data 54 PBPU7 FROM MOR1 DATA DIRECTION REGISTER B BIT DDRB7 PORT B DATA REGISTER BIT PB7 ...

  • Page 55

    ... Freescale Semiconductor, Inc. 4.3.4 Capture/Compare Timer Interrupts Setting the I bit in the CCR disables all interrupts except for SWI. 4.3.5 SCI Interrupts The serial communications interface (SCI) can generate these interrupts: • • • • • Setting the I bit in the CCR disables all SCI interrupts. ...

  • Page 56

    ... Freescale Semiconductor, Inc. Interrupts • • 4.3.6 SPI Interrupts The serial peripheral interrupt (SPI) can generate these interrupts: • • Setting the I bit in the CCR disables all SPI interrupts. • • Technical Data 56 SCI Receiver Overrun Interrupt — The overrun bit (OR) indicates that a received byte is lost because software has not read the previously received byte ...

  • Page 57

    ... Freescale Semiconductor, Inc. 4.4 Interrupt Processing The CPU takes these actions to begin servicing an interrupt: 1. Stores the CPU registers on the stack in the order shown in 2. Sets the I bit in the CCR to prevent further interrupts 3. Loads the program counter with the contents of the appropriate ...

  • Page 58

    ... Freescale Semiconductor, Inc. Interrupts STACKING ORDER NOTE: If more than one interrupt request is pending, the CPU fetches the vector of the higher priority interrupt first. A higher priority interrupt does not interrupt a lower priority interrupt service routine unless the lower priority interrupt service routine clears the I bit. See listing ...

  • Page 59

    ... Freescale Semiconductor, Inc. FROM RESET I BIT IN YES CCR REGISTER EXTERNAL INTERRUPT? TIMER INTERRUPT? INTERRUPT? INTERRUPT? FETCH NEXT INSTRUCTION INSTRUCTION? INSTRUCTION? Figure 4-5. Reset and Interrupt Processing Flowchart MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, SET? NO YES IRQ CLEAR IRQ REQUEST LATCH ...

  • Page 60

    ... Freescale Semiconductor, Inc. Interrupts Technical Data 60 Interrupts For More Information On This Product, Go to: www.freescale.com MC68HC705C8A — Rev. 3 MOTOROLA ...

  • Page 61

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705C8A 5.1 Contents 5.2 5.3 5.3.1 5.3.2 5.3.3 5.3.3.1 5.3.3.2 5.3.4 5.2 Introduction This section describes how resets initialize the microcontroller unit (MCU). 5.3 Reset Sources A reset immediately stops the operation of the instruction being executed, initializes certain control bits, and loads the program counter with a user-defined reset vector address ...

  • Page 62

    ... Freescale Semiconductor, Inc. Resets 5.3.1 Power-On Reset (POR) A positive transition on the V The POR is strictly for the power-up condition and cannot be used to detect drops in power supply voltage. A 4064 t active allows the clock generator to stabilize. If the RESET pin is at logic 0 at the end of 4064 t until the signal on the RESET pin goes to logic 1 ...

  • Page 63

    ... Freescale Semiconductor, Inc. 5.3.3.1 Programmable COP Watchdog Reset A timeout of the 18-stage ripple counter in the programmable COP watchdog generates a reset. programmable COP watchdog. Two registers control and monitor operation of the programmable COP watchdog: • • To clear the programmable COP watchdog and begin a new timeout period, write these values to the COP reset register (COPRST) ...

  • Page 64

    ... Freescale Semiconductor, Inc. Resets Address: Read: Write: Reset: Figure 5-2. Programmable COP Reset Register (COPRST) The programmable COP control register (COPCR) shown in does these functions: • • • • Address: Read: Write: Reset: Figure 5-3. Programmable COP Control Register (COPCR) COPF — COP Flag ...

  • Page 65

    ... Freescale Semiconductor, Inc. CME — Clock Monitor Enable Bit This read/write bit enables the clock monitor. The clock monitor sets the COPF bit and generates a reset if it detects an absent internal clock for a period of from 100 s. CME is readable and writable at any time. Reset clears the CME bit. ...

  • Page 66

    ... Freescale Semiconductor, Inc. Resets Table 5-1. Programmable COP Timeout Period Selection COP CM1:CM0 Timeout Rate 5.3.3.2 Non-Programmable COP Watchdog A timeout of the 18-stage ripple counter in the non-programmable COP watchdog generates a reset. The timeout period is 65.536 ms when f OSC is a direct function of the crystal frequency. The equation is: ...

  • Page 67

    ... Freescale Semiconductor, Inc. 2. COP clear bit (COPC) at address $1FF0 NOTE: The non-programmable watchdog COP is disabled in bootloader mode, even if the NCOPE bit is programmed. Figure 5-4 NON-PROGRAMMABLE COP WATCHDOG (MC68HC05C4A TYPE) 5.3.4 Clock Monitor Reset When the CME bit in the COP control register is set, the clock monitor detects the absence of the internal bus clock for a certain period of time ...

  • Page 68

    ... Freescale Semiconductor, Inc. Resets The clock monitor is a useful backup to the COP watchdog system. Because the watchdog timer requires a clock to function, it cannot indicate a system clock failure. The clock monitor would detect such a condition and force the MCU to a reset state. Clocks are not required for the MCU to reach a reset condition ...

  • Page 69

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705C8A 6.1 Contents 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.4 6.4.1 6.4.2 6.5 6.2 Introduction This section describes the three low-power modes: • • • 6.3 Stop Mode The STOP instruction places the microcontroller unit (MCU) in its lowest power consumption mode ...

  • Page 70

    ... Freescale Semiconductor, Inc. Low-Power Modes STOP OSCILLATOR AND ALL CLOCKS CLEAR I BIT NO RESET EXTERNAL INTERRUPT (IRQ) NO YES TURN ON OSCILLATOR WAIT FOR TIME DELAY TO STABILIZE 1. FETCH RESET VECTOR 2. SERVICE INTERRUPT: a. STACK b. SET I BIT c. VECTOR TO INTERRUPT ROUTINE Figure 6-1. Stop/Wait Mode Function Flowchart During stop mode, the I bit in the condition code register (CCR) is cleared to enable external interrupts ...

  • Page 71

    ... Freescale Semiconductor, Inc. 6.3.1 SCI During Stop Mode When the MCU enters stop mode, the baud rate generator stops, halting all SCI activity. If the STOP instruction is executed during a transmitter transfer, that transfer is halted low input to the IRQ pin is used to exit stop mode, the transfer resumes. ...

  • Page 72

    ... Freescale Semiconductor, Inc. Low-Power Modes NOTE: If the clock monitor is enabled (CME = 1), the STOP instruction causes the clock monitor to time out and reset the MCU. Technical Data 72 STOP CLEAR I BIT IN CCR TURN OFF INTERNAL OSCILLATOR SUSPEND COP COUNTER YES EXTERNAL RESET EXTERNAL ...

  • Page 73

    ... Freescale Semiconductor, Inc. 6.3.4 Non-Programmable COP Watchdog in Stop Mode The STOP instruction has these effects on the non-programmable COP watchdog: • • If the RESET pin brings the MCU out of stop mode, the COP watchdog begins counting immediately. The reset function clears the COP counter ...

  • Page 74

    ... Freescale Semiconductor, Inc. Low-Power Modes Technical Data 74 STOP CLEAR I BIT IN CCR CLEAR COP COUNTER TURN OFF INTERNAL OSCILLATOR TURN OFF COP COUNTER YES EXTERNAL RESET EXTERNAL INTERRUPT? YES TURN ON INTERNAL OSCILLATOR TURN ON COP WATCHDOG YES END OF STABILIZATION DELAY? NO TURN ON INTERNAL CLOCK 1 ...

  • Page 75

    ... Freescale Semiconductor, Inc. 6.4.1 Programmable COP Watchdog in Wait Mode The programmable COP watchdog is active during wait mode. Software must periodically bring the MCU out of wait mode to clear the programmable COP watchdog. 6.4.2 Non-Programmable COP Watchdog in Wait Mode The non-programmable COP watchdog is active during wait mode. ...

  • Page 76

    ... Freescale Semiconductor, Inc. Low-Power Modes Technical Data 76 Low-Power Modes For More Information On This Product, Go to: www.freescale.com MC68HC705C8A — Rev. 3 MOTOROLA ...

  • Page 77

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705C8A 7.1 Contents 7.2 7.3 7.3.1 7.3.2 7.3.3 7.4 7.4.1 7.4.2 7.4.3 7.5 7.5.1 7.5.2 7.5.3 7.6 7.2 Introduction This section describes the programming of ports and D. MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, Section 7 ...

  • Page 78

    ... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) 7.3 Port A Port 8-bit, general-purpose, bidirectional input/output (I/O) port. 7.3.1 Port A Data Register The port A data register (PORTA) shown in latch for each of the eight port A pins. When a port A pin is programmed output, the state of its data register bit determines the state of the output pin ...

  • Page 79

    ... Freescale Semiconductor, Inc. 7.3.2 Data Direction Register A The contents of data direction register A (DDRA) shown in determine whether each port A pin is an input or an output. Writing a logic DDRA bit enables the output buffer for the associated port A pin; a logic 0 disables the output buffer. A reset clears all DDRA bits, configuring all port A pins as inputs ...

  • Page 80

    ... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) 7.3.3 Port A Logic Figure 7-3 When a port A pin is programmed output, the state of its data register bit determines the state of the output pin. When a port A pin is programmed input, reading the port A data register returns the logic state of the pin. ...

  • Page 81

    ... Freescale Semiconductor, Inc. 7.4 Port B Port 8-bit, general-purpose, bidirectional I/O port. Port B pins can also be configured to function as external interrupts. The port B pullup devices are enabled in mask option register 1 (MOR1). See Option Register 1 7.4.1 Port B Data Register The port B data register (PORTB) shown in latch for each of the eight port B pins ...

  • Page 82

    ... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) 7.4.2 Data Direction Register B The contents of data direction register B (DDRB) shown in determine whether each port B pin is an input or an output. Writing a logic DDRB bit enables the output buffer for the associated port B pin; a logic 0 disables the output buffer. A reset clears all DDRB bits, configuring all port B pins as inputs ...

  • Page 83

    ... Freescale Semiconductor, Inc. 7.4.3 Port B Logic Figure 7-6 READ $0005 WRITE $0005 RESET WRITE $0001 READ $0001 IRQ FROM OPTION REGISTER FROM OTHER PORT B PINS IRQ RESET EXTERNAL INTERRUPT VECTOR FETCH MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, shows the port B I/O logic. ...

  • Page 84

    ... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) When a port B pin is programmed as an output, reading the port bit reads the value of the data latch and not the voltage on the pin itself. When a port B pin is programmed as an input, reading the port bit reads the voltage level on the pin ...

  • Page 85

    ... Freescale Semiconductor, Inc. 7.5 Port C Port 8-bit, general-purpose, bidirectional I/O port. PC7 has a high current sink and source capability. 7.5.1 Port C Data Register The port C data register (PORTC) shown in latch for each of the eight port C pins. When a port C pin is programmed output, the state of its data register bit determines the state of the output pin ...

  • Page 86

    ... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) 7.5.2 Data Direction Register C The contents of data direction register C (DDRC) shown in determine whether each port C pin is an input or an output. Writing a logic DDRC bit enables the output buffer for the associated port C pin; a logic 0 disables the output buffer. A reset clears all DDRC bits, configuring all port C pins as inputs ...

  • Page 87

    ... Freescale Semiconductor, Inc. 7.5.3 Port C Logic Figure 7-9 When a port C pin is programmed as an output, reading the port bit reads the value of the data latch and not the voltage on the pin. When a port C pin is programmed as an input, reading the port bit reads the voltage level on the pin ...

  • Page 88

    ... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) 7.6 Port D Port 7-bit, special-purpose, input-only port that has no data register. Reading address $0003 returns the logic states of the port D pins. Port D shares pins PD5–PD2 with the serial peripheral interface module (SPI). When the SPI is enabled, PD5–PD2 read as logic 0s. When the SPI is disabled, reading address $0003 returns the logic states of the PD5– ...

  • Page 89

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705C8A 8.1 Contents 8.2 8.3 8.3.1 8.3.2 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.2 Introduction This section describes the operation of the 16-bit capture/compare timer. Figure 8-1 summary of the timer input/output (I/O) registers. 8.3 Timer Operation The core of the capture/compare timer is a 16-bit free-running counter ...

  • Page 90

    ... Freescale Semiconductor, Inc. Capture/Compare Timer EDGE SELECT/ TCAP DETECT LOGIC $0012 TIMER CONTROL REGISTER Technical Data 90 ICRH ($0014) ICRL ($0015) TRH ($0018) TRL ($0019) 16-BIT COUNTER 16-BIT COMPARATOR OCRH ($0016) OCRL ($0017) TIMER STATUS REGISTER INTERNAL DATA BUS Figure 8-1. Timer Block Diagram ...

  • Page 91

    ... Freescale Semiconductor, Inc. Addr. Register Name Read: Timer Control Register $0012 (TCR) See page 94. Reset: Read: Timer Status Register $0013 (TSR) See page 96. Reset: Read: Bit 15 Input Capture Register $0014 High (ICRH) See page 100. Reset: Read: Input Capture Register $0015 Low (ICRL) See page 100 ...

  • Page 92

    ... Freescale Semiconductor, Inc. Capture/Compare Timer Because of the 16-bit timer architecture, the I/O registers for the input capture and output compare functions are pairs of 8-bit registers. Because the counter is 16 bits long and preceded by a fixed divide-by-four prescaler, the counter rolls over every 262,144 internal clock cycles ...

  • Page 93

    ... Freescale Semiconductor, Inc. 8.3.2 Output Compare The output compare function can generate an output signal when the 16-bit counter reaches a selected value. Software writes the selected value into the output compare registers. On every fourth internal clock cycle the output compare circuitry compares the value of the counter to the value written in the output compare registers ...

  • Page 94

    ... Freescale Semiconductor, Inc. Capture/Compare Timer 8.4 Timer I/O Registers These registers control and monitor the timer operation: • • • • • • 8.4.1 Timer Control Register The timer control register (TCR) as shown in functions: • • • • • Address: Read: ...

  • Page 95

    ... Freescale Semiconductor, Inc. ICIE — Input Capture Interrupt Enable Bit This read/write bit enables interrupts caused by an active signal on the TCAP pin. Reset clears the ICIE bit. OCIE — Output Compare Interrupt Enable Bit This read/write bit enables interrupts caused by an active signal on the TCMP pin. Reset clears the OCIE bit. TOIE — ...

  • Page 96

    ... Freescale Semiconductor, Inc. Capture/Compare Timer 8.4.2 Timer Status Register The timer status register (TSR read-only register shown in Figure 8-6 • • • Address: Read: Write: Reset: ICF — Input Capture Flag The ICF bit is set automatically when an edge of the selected polarity occurs on the TCAP pin ...

  • Page 97

    ... Freescale Semiconductor, Inc. TOF — Timer Overflow Flag The TOF bit is automatically set when the 16-bit counter rolls over from $FFFF to $0000. Clear the TOF bit by reading the timer status register with TOF set and then reading the low byte ($0019) of the timer registers. Reset has no effect on TOF. Bits 4– ...

  • Page 98

    ... Freescale Semiconductor, Inc. Capture/Compare Timer Reading TRH returns the current value of the high byte of the counter and causes the low byte to be latched into a buffer, as shown in Figure more than once. Reading TRL reads the transparent low byte buffer and completes the read sequence of the timer registers. ...

  • Page 99

    ... Freescale Semiconductor, Inc. Register Name and Address: Alternate Timer Register High — $001A Read: Write: Reset: Register Name and Address: Alternate Timer Register Low — $001B Read: Write: Reset: Figure 8-9. Alternate Timer Registers (ATRH and ATRL) Reading ATRH returns the current value of the high byte of the counter ...

  • Page 100

    ... Freescale Semiconductor, Inc. Capture/Compare Timer 8.4.5 Input Capture Registers When a selected edge occurs on the TCAP pin, the current high and low bytes of the 16-bit counter are latched into the read-only input capture registers (ICRH and ICRL) shown in reading ICRL inhibits further captures until ICRL is read. Reading ICRL after reading the timer status register clears the input capture flag (ICF) ...

  • Page 101

    ... Freescale Semiconductor, Inc. 8.4.6 Output Compare Registers When the value of the 16-bit counter matches the value in the read/write output compare registers (OCRH and OCRL) shown in planned TCMP pin action takes place. Writing to OCRH before writing to OCRL inhibits timer compares until OCRL is written. Reading or writing to OCRL after reading the timer status register clears the output compare flag (OCF) ...

  • Page 102

    ... Freescale Semiconductor, Inc. Capture/Compare Timer Technical Data 102 Capture/Compare Timer For More Information On This Product, Go to: www.freescale.com MC68HC705C8A — Rev. 3 MOTOROLA ...

  • Page 103

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705C8A 9.1 Contents 9.2 9.3 9.3.1 9.3.2 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 9.4.7 9.4.8 9.5 9.5.1 9.5.2 9.5.3 9.6 9.2 Introduction This section describes erasable, programmable read-only memory/one-time programmable read-only memory (EPROM/OTPROM (PROM)) programming. ...

  • Page 104

    ... Freescale Semiconductor, Inc. EPROM/OTPROM (PROM) 9.3 EPROM/OTPROM (PROM) Programming The internal PROM can be programmed efficiently using the Motorola MC68HC05PGMR-2 programmer board, which can be purchased from a Motorola-authorized distributor. The user can program the microcontroller unit (MCU) using this printed circuit board (PCB) in conjunction with an EPROM device already programmed with user code ...

  • Page 105

    ... Freescale Semiconductor, Inc. MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, START APPLY V NTRYS = 0 START AT BEGINNING OF MEMORY LAT = 1 WRITE PROM DATA PGM = 1 WAIT 1 ms PGM = 0 LAT = 0 YES WRITE ADDITIONAL NTRYS = NTRYS + 1 NO NTRYS = 2 V Figure 9-1. EPROM/OTPROM Programming Flowchart EPROM/OTPROM (PROM) Go to: www ...

  • Page 106

    ... Freescale Semiconductor, Inc. EPROM/OTPROM (PROM + – GND 1 P3 RXD 3 TXD 2 CTS 5 DSR 6 DCD 8 DTR 20 GND 1 GND 7 Notes: 1. The asterisk (*) denotes option T command only. 2. Unless otherwise specified, resistors are in ohms, 5% 1/4 W; capacitors are in F; voltages are dc. 3. Device type numbers shown in circuit are for reference only ...

  • Page 107

    ... Freescale Semiconductor, Inc 2.0 MHz R10* 470 VERF DS2* (VERF) M (PROG) N PROG DS1* (A5) (A4) (A3) R11* (A2) 470 (A1) (A0 (D0) (D1) (D2) (D3) (D4 Figure 9-2. PROM Programming Circuit (Continued) MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product R13 PA5 PD7 8 PA4 TCMP 9 PA3 PD5 ...

  • Page 108

    ... Freescale Semiconductor, Inc. EPROM/OTPROM (PROM) To program the PROM MCU, the MCU is installed in the PCB, along with an EPROM device programmed with user code; the MCU is then subjected to a series of routines. The routines necessary to program, verify, and secure the PROM MCU are: • ...

  • Page 109

    ... Freescale Semiconductor, Inc. 9.3.1 Program Register The program register (PROG) shown in programming. Address: Read: Write: Reset: LAT — Latch Enable Bit This bit is both readable and writable. PGM — Program Bit If LAT is cleared, PGM cannot be set. Bits 1 and 3 7 — Not used; always read 0 MC68HC705C8A — ...

  • Page 110

    ... Freescale Semiconductor, Inc. EPROM/OTPROM (PROM) 9.3.2 Preprogramming Steps Before programming the PROM using an MC68HC05PGMR PCB in standalone mode, the user should ensure that: • • • • • NOTE: If the V MCU device will suffer permanent damage. Once those conditions are met, the user should take these steps before beginning programming: 1 ...

  • Page 111

    ... Freescale Semiconductor, Inc. 9.4 PROM Programming Routines This subsection describes the routines necessary to program, verify, and secure the PROM device, and other routines available to the user. 9.4.1 Program and Verify PROM The program and verify PROM routine copies the contents of the external EPROM into the MCU PROM with direct correspondence between the addresses ...

  • Page 112

    ... Freescale Semiconductor, Inc. EPROM/OTPROM (PROM) 9.4.2 Verify PROM Contents The verify PROM contents routine is normally run automatically after the PROM is programmed. Direct entry to this routine causes the PROM contents of the MCU to be compared to the contents of the external memory locations of the EPROM at the same addresses. ...

  • Page 113

    ... Freescale Semiconductor, Inc. 9.4.4 Secure PROM and Verify This routine is used after the PROM is programmed successfully to verify the contents of the MCU PROM against the contents of the EPROM and then to secure the PROM. To accomplish this routine, take these steps: 1. Set switch 1 in the ON position (restores V 2 ...

  • Page 114

    ... Freescale Semiconductor, Inc. EPROM/OTPROM (PROM) No LED is illuminated during this routine. Further, the end of the routine does not mean that the SEC bit was verified. To ensure that security is properly enabled, attempt to perform another verify routine. If the green LED does not light, the PROM has been secured properly. ...

  • Page 115

    ... Freescale Semiconductor, Inc. 9.4.7 Execute Program in RAM This routine allows the MCU to transfer control to a program previously loaded in RAM. This program is executed once bootstrap mode is entered, if switch the ON position and switch the OUT position, without any firmware initialization. The program must start at location $0051 to be compatible with the load program in RAM routine ...

  • Page 116

    ... Freescale Semiconductor, Inc. EPROM/OTPROM (PROM) 9.5 Control Registers This subsection describes the three registers that control memory configuration, PROM security, and IRQ edge or level sensitivity; port B pullups; and non-programmable COP enable/disable. 9.5.1 Option Register The option register shown in sensitivity, enable the PROM security, and select the memory configuration ...

  • Page 117

    ... Freescale Semiconductor, Inc. SEC — Security Bit This bit is implemented as an EPROM cell and is not affected by reset. IRQ — Interrupt Request Pin Sensitivity Bit IRQ is set only by reset, but can be cleared by software. This bit can only be written once. Bits 5, 4, and 0 — Not used; always read 0 Bit 2 — ...

  • Page 118

    ... Freescale Semiconductor, Inc. EPROM/OTPROM (PROM) NOTE: PBPU0/COPC programmed enables the port B pullup bit. This bit is also used to clear the non-programmable COP (MC68HC05C4A type). Writing to this bit to clear the COP will not affect the state of the port B pull-up (bit 0). See Non-Programmable COP Watchdog ...

  • Page 119

    ... Freescale Semiconductor, Inc. 9.6 EPROM Erasing The erased state of an EPROM or OTPROM byte is $00. EPROM devices can be erased by exposure to a high intensity ultraviolet (UV) light with a wave length of 2537 Å. The recommended erasure dosage (UV intensity on a given surface area x exposure time Ws/cm lamps should be used without short-wave filters, and the EPROM device should be positioned about one inch from the UV source ...

  • Page 120

    ... Freescale Semiconductor, Inc. EPROM/OTPROM (PROM) Technical Data 120 EPROM/OTPROM (PROM) For More Information On This Product, Go to: www.freescale.com MC68HC705C8A — Rev. 3 MOTOROLA ...

  • Page 121

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705C8A Section 10. Serial Communications Interface (SCI) 10.1 Contents 10.2 10.3 10.4 10.5 10.5.1 10.5.2 10.6 10.6.1 10.6.2 10.6.3 10.6.4 10.6.5 10.2 Introduction The serial communications interface (SCI) module allows high-speed asynchronous communication with peripheral devices and other microcontroller units (MCUs). MC68HC705C8A — ...

  • Page 122

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 10.3 Features Features of the SCI module include: • • • • • • • • • 10.4 SCI Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in Technical Data 122 Standard mark/space non-return-to-zero format ...

  • Page 123

    ... Freescale Semiconductor, Inc. START BIT 0 BIT 1 BIT START BIT 0 BIT 1 BIT 10.5 SCI Operation The SCI allows full-duplex, asynchronous, RS232 or RS422 serial communication between the MCU and remote devices, including other MCUs. The transmitter and receiver of the SCI operate independently, although they use the same baud-rate generator. This subsection describes the operation of the SCI transmitter and receiver ...

  • Page 124

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 1X BAUD RATE CLOCK SCCR1 ($000E) SCI RECEIVE REQUESTS SCI INTERRUPT REQUEST Technical Data 124 SCDR ($0011) TRANSMIT SHIFT REGISTER TRANSMITTER CONTROL LOGIC SCSR ($0010) TDRE TIE TC TCIE SCCR2 ($000F) Figure 10-2. SCI Transmitter Serial Communications Interface (SCI) For More Information On This Product, Go to: www ...

  • Page 125

    ... Freescale Semiconductor, Inc. Addr. Register Name Read: Baud Rate Register $000D (Baud) See page 136. Reset: Read: SCI Control Register 1 $000E (SCCR1) See page 130. Reset: Read: SCI Control Register 2 $000F (SCCR2) See page 131. Reset: Read: TDRE SCI Status Register ...

  • Page 126

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) • • • Technical Data 126 Break Characters — Writing a logic 1 to the SBK bit in SCCR2 loads the shift register with a break character. A break character contains all logic 0s and has no start and stop bits. Break character length depends on the M bit in SCCR1 ...

  • Page 127

    ... Freescale Semiconductor, Inc. 10.5.2 Receiver Figure 10-4 Figure 10-3 16X BAUD RATE CLOCK PD0/ PIN BUFFER RDI AND CONTROL M SCCR1 ($000E) SCI TRANSMIT REQUESTS SCI INTERRUPT REQUEST MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, shows the structure of the SCI receiver. Refer to for a summary of the SCI receiver I/O registers ...

  • Page 128

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) • • • • Technical Data 128 Character Length — The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCCR1) determines character length. When receiving 9-bit data, bit R8 in SCCR1 is the ninth bit (bit 8). ...

  • Page 129

    ... Freescale Semiconductor, Inc. • • 10.6 SCI I/O Registers These I/O registers control and monitor SCI operation: • • • • 10.6.1 SCI Data Register The SCI data register (SCDR) shown in characters received and for characters transmitted. Address: Read: Write: Reset: MC68HC705C8A — ...

  • Page 130

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 10.6.2 SCI Control Register 1 SCI control register 1 (SCCR1) shown in functions: • • • Address: Read: Write: Reset: R8 — Bit 8 (Received) When the SCI is receiving 9-bit characters the ninth bit of the received character. R8 receives the ninth bit at the same time that the SCDR receives the other eight bits. Reset has no effect on the R8 bit. T8 — ...

  • Page 131

    ... Freescale Semiconductor, Inc. WAKE — Wakeup Bit This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition of the PD0/RDI pin. Reset has no effect on the WAKE bit. 10.6.3 SCI Control Register 2 ...

  • Page 132

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) TCIE — Transmission Complete Interrupt Enable Bit This read/write bit enables SCI interrupt requests when the TC bit becomes set. Reset clears the TCIE bit. RIE — Receive Interrupt Enable Bit This read/write bit enables SCI interrupt requests when the RDRF bit or the OR bit becomes set. Reset clears the RIE bit. ILIE — ...

  • Page 133

    ... Freescale Semiconductor, Inc. idle input or an address mark brings the receiver out of the standby state. Reset clears the RWU bit. SBK — Send Break Bit Setting this read/write bit continuously transmits break codes in the form of 10-bit or 11-bit groups of logic 0s. Clearing the SBK bit stops the break codes and transmits a logic start bit ...

  • Page 134

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) TDRE — Transmit Data Register Empty Bit This clearable, read-only bit is set when the data in the SCDR transfers to the transmit shift register. TDRE generates an interrupt request if the TIE bit in SCCR2 is also set. Clear the TDRE bit by reading the SCSR with TDRE set and then writing to the SCDR ...

  • Page 135

    ... Freescale Semiconductor, Inc. OR — Receiver Overrun Bit This clearable, read-only bit is set if the SCDR is not read before the receive shift register receives the next word. OR generates an interrupt request if the RIE bit in SCCR2 is also set. The data in the shift register is lost, but the data already in the SCDR is not affected. ...

  • Page 136

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 10.6.5 Baud Rate Register The baud rate register shown in both the receiver and the transmitter. Address: Read: Write: Reset: SCP1 and SCP0 — SCI Prescaler Select Bits These read/write bits control prescaling of the baud rate generator ...

  • Page 137

    ... Freescale Semiconductor, Inc. SCR2–SCR0 — SCI Baud Rate Select Bits Table 10-3 frequencies of 2 MHz, 4 MHz, and 4.194304 MHz. MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, These read/write bits select the SCI baud rate, as shown in Table 10-2. Reset has no effect on the SCR2–SCR0 bits. ...

  • Page 138

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) SCP[1: Technical Data 138 Table 10-3. Baud Rate Selection Examples SCR[2:1: MHz OSC 000 62.50 Kbaud 001 31.25 Kbaud 010 15.63 Kbaud 011 7813 baud 100 3906 baud 101 1953 baud 110 976.6 baud 111 488 ...

  • Page 139

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705C8A Section 11. Serial Peripheral Interface (SPI) 11.1 Contents 11.2 11.3 11.4 11.4.1 11.4.2 11.5 11.6 11.7 11.7.1 11.7.2 11.7.3 11.8 11.9 11.9.1 11.9.2 11.9.3 11.2 Introduction The serial peripheral interface (SPI) module allows full-duplex, synchronous, serial communication with peripheral devices. ...

  • Page 140

    ... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 11.3 Features Features of the SPI include: • • • • • • • • Figure 11-1 summary of the SPI input/output (I/O) registers. Technical Data 140 Full-duplex operation Master and slave modes Four programmable master mode frequencies (1.05 MHz maximum) 2 ...

  • Page 141

    ... Freescale Semiconductor, Inc. INTERNAL CLOCK (XTAL 2) DIVIDER SPI CLOCK (MASTER) SELECT SPI CONTROL SPSR ($000B) SPI INTERRUPT REQUEST MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, SPI SHIFT REGISTER SPDR ($000C) MSTR SPE SPIE SPCR ($000A) INTERNAL DATA BUS Figure 11-1. SPI Block Diagram Serial Peripheral Interface (SPI) Go to: www ...

  • Page 142

    ... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Addr. Register Name SPI Control Register $000A (SPCR) See page 149. SPI Status Register $000B (SPSR) See page 151. SPI Data Register $000C (SPDR) See page 149. Figure 11-2. SPI I/O Register Summary 11.4 Operation ...

  • Page 143

    ... Freescale Semiconductor, Inc slave SPI, data enters the shift register under the control of the serial clock from the master SPI. After a byte enters the shift register of a slave SPI, it transfers to the SPDR. To prevent an overrun condition, slave software must then read the byte in the SPDR before another byte enters the shift register and is ready to transfer to the SPDR ...

  • Page 144

    ... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 11.4.2 Pin Functions in Slave Mode Clearing the MSTR bit in the SPCR configures the SPI for operation in slave mode. The slave-mode functions of the SPI pins are: • • • • When CPHA = 0, the shift clock is the with SCK. In this clock phase mode, SS must go high between successive characters in an SPI message ...

  • Page 145

    ... Freescale Semiconductor, Inc. Example: LDA #$1C STA SPCR LDA #$4C STA SPCR 11.5 Multiple-SPI Systems In a multiple-SPI system, all PD4/SCK pins are connected together, all PD3/MOSI pins are connected together, and all PD2/MISO pins are connected together. Before a transmission, one SPI is configured as master and the rest are configured as slaves ...

  • Page 146

    ... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Figure 11-5. Two Master/Slaves and Three Slaves Block Diagram 11.6 Serial Clock Polarity and Phase To accommodate the different serial communication requirements of peripheral devices, software can change the phase and polarity of the SPI serial clock. The clock polarity bit (CPOL) and the clock phase bit (CPHA), both in the SPCR, control the timing relationship between the serial clock and the transmitted data ...

  • Page 147

    ... Freescale Semiconductor, Inc. 11.7 SPI Error Conditions These conditions produce SPI system errors: • • • 11.7.1 Mode Fault Error A mode fault error results when a logic 0 occurs on the PD5/SS pin of a master SPI. The MCU takes these actions when a mode fault error occurs: • ...

  • Page 148

    ... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 11.7.3 Overrun Error Failing to read the byte in the SPDR before a subsequent byte enters the shift register causes an overrun condition overrun condition, all incoming data is lost until software clears SPIF. The overrun condition has no flag. ...

  • Page 149

    ... Freescale Semiconductor, Inc. 11.9.1 SPI Data Register The SPDR shown in received by the SPI. Writing a byte to the SPDR places the byte directly into the SPI shift register. Address: Read: Write: Reset: 11.9.2 SPI Control Register • • • • Address: Read: Write: Reset: SPIE — ...

  • Page 150

    ... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) SPI — SPI Enable Bit This read/write bit enables the SPI. Reset clears the SPE bit. MSTR — Master Bit This read/write bit selects master mode operation or slave mode operation. Reset clears the MSTR bit. ...

  • Page 151

    ... Freescale Semiconductor, Inc. 11.9.3 SPI Status Register The SPSR shown in conditions: • • • Address: Read: Write: Reset: SPIF — SPI Flag This clearable, read-only bit is set each time a byte shifts out of or into the shift register. SPIF generates an interrupt request if the SPIE bit in the SPCR is also set ...

  • Page 152

    ... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) MODF — Mode Fault Bit This clearable, read-only bit is set when a logic 0 occurs on the PD5/SS pin while the MSTR bit is set. MODF generates an interrupt request if the SPIE bit is also set. Clear the MODF bit by reading the SPSR with MODF set and then writing to the SPCR ...

  • Page 153

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705C8A 12.1 Contents 12.2 12.3 12.3.1 12.3.2 12.3.3 12.3.4 12.3.5 12.3.6 12.3.7 12.3.8 12.4 12.4.1 12.4.2 12.4.3 12.4.4 12.4.5 12.5 12.6 MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, Section 12. Instruction Set Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Addressing Modes ...

  • Page 154

    ... Freescale Semiconductor, Inc. Instruction Set 12.2 Introduction The MCU instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X) ...

  • Page 155

    ... Freescale Semiconductor, Inc. 12.3.1 Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long ...

  • Page 156

    ... Freescale Semiconductor, Inc. Instruction Set 12.3.5 Indexed, No Offset Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000– ...

  • Page 157

    ... Freescale Semiconductor, Inc. 12.3.8 Relative Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two’ ...

  • Page 158

    ... Freescale Semiconductor, Inc. Instruction Set 12.4.1 Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Technical Data 158 Table 12-1. Register/Memory Instructions ...

  • Page 159

    ... Freescale Semiconductor, Inc. 12.4.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. NOTE: Do not use read-modify-write operations on write-only registers. MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, Table 12-2 ...

  • Page 160

    ... Freescale Semiconductor, Inc. Instruction Set 12.4.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met ...

  • Page 161

    ... Freescale Semiconductor, Inc. MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, Table 12-3. Jump and Branch Instructions Instruction Branch if carry bit clear Branch if carry bit set Branch if equal Branch if half-carry bit clear Branch if half-carry bit set Branch if higher Branch if higher or same ...

  • Page 162

    ... Freescale Semiconductor, Inc. Instruction Set 12.4.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations ...

  • Page 163

    ... Freescale Semiconductor, Inc. 12.4.5 Control Instructions These instructions act on CPU registers and control CPU operation during program execution. MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, Table 12-5. Control Instructions Instruction Clear carry bit Clear interrupt mask No operation Reset stack pointer ...

  • Page 164

    ... Freescale Semiconductor, Inc. Instruction Set 12.5 Instruction Set Summary Table 12-6. Instruction Set Summary (Sheet Source Operation Form ADC #opr ADC opr ADC opr Add with Carry ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr Add without Carry ...

  • Page 165

    ... Freescale Semiconductor, Inc. Table 12-6. Instruction Set Summary (Sheet Source Operation Form BIH rel Branch if IRQ Pin High BIL rel Branch if IRQ Pin Low BIT #opr BIT opr BIT opr Bit Test Accumulator with Memory Byte BIT opr,X BIT opr,X BIT ,X ...

  • Page 166

    ... Freescale Semiconductor, Inc. Instruction Set Table 12-6. Instruction Set Summary (Sheet Source Operation Form CLR opr CLRA CLRX Clear Byte CLR opr,X CLR ,X CMP #opr CMP opr CMP opr Compare Accumulator with Memory Byte CMP opr,X CMP opr,X CMP ,X COM opr ...

  • Page 167

    ... Freescale Semiconductor, Inc. Table 12-6. Instruction Set Summary (Sheet Source Operation Form JSR opr JSR opr JSR opr,X Jump to Subroutine JSR opr,X JSR ,X LDA #opr LDA opr LDA opr Load Accumulator with Memory Byte LDA opr,X LDA opr,X LDA ,X LDX #opr ...

  • Page 168

    ... Freescale Semiconductor, Inc. Instruction Set Table 12-6. Instruction Set Summary (Sheet Source Operation Form ROR opr RORA RORX Rotate Byte Right through Carry Bit ROR opr,X ROR ,X RSP Reset Stack Pointer RTI Return from Interrupt RTS Return from Subroutine SBC #opr ...

  • Page 169

    ... Freescale Semiconductor, Inc. Table 12-6. Instruction Set Summary (Sheet Source Operation Form TST opr TSTA TSTX Test Memory Byte for Negative or Zero TST opr,X TST ,X TXA Transfer Index Register to Accumulator WAIT Stop CPU Clock and Enable Interrupts A Accumulator C Carry/borrow flag CCR ...

  • Page 170

    ... Freescale Semiconductor, Inc. Instruction Set Technical Data 170 Instruction Set For More Information On This Product, Go to: www.freescale.com MC68HC705C8A — Rev. 3 MOTOROLA ...

  • Page 171

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705C8A 13.1 Contents 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 13.10 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 13.11 5.0-Volt Serial Peripheral Interface (SPI) Timing . . . . . . . . . . 185 13.12 3.3-Volt Serial Peripheral Interface (SPI) Timing . . . . . . . . . . 187 13.2 Introduction This section contains electrical and timing specifications. ...

  • Page 172

    ... Freescale Semiconductor, Inc. Electrical Specifications 13.3 Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table here ...

  • Page 173

    ... Freescale Semiconductor, Inc. 13.4 Operating Temperature Range Operating temperature range MC68HC705C8ACB MC68HC705C8ACFB MC68HC705C8ACFS MC68HC705C8ACP MC68HC705C8ACFN MC68HC705C8ACFS 1. Voltages referenced Extended temperature range (– Plastic dual in-line package (PDIP Plastic shrink dual in-line package (SDIP Ceramic dual in-line package (cerdip Plastic-leaded chip carrier (PLCC) ...

  • Page 174

    ... Freescale Semiconductor, Inc. Electrical Specifications 13.6 Power Considerations The average chip junction temperature, T Where For most applications, P Ignoring P Solving equations (1) and (2) for K gives: where constant pertaining to the particular part. K can be determined from equation (3) by measuring P known T by solving equations (1) and (2) iteratively for any value of T ...

  • Page 175

    ... Freescale Semiconductor, Inc. 13.7 5.0-Volt DC Electrical Characteristics Characteristic Output voltage, I 10.0 A Load Output high voltage I = –0.8 mA, PA7–PA0, PB7–PB0, PC6–PC0, TCMP Load (see Figure 13- –1.6 mA, PD4–PD1 (see Load I = –5.0 mA, PC7 Load Output low voltage (see Figure 13- 1.6 mA Load PA7– ...

  • Page 176

    ... Freescale Semiconductor, Inc. Electrical Specifications 13.8 3.3-Volt DC Electrical Characteristics Characteristic Output voltage, I 10.0 A Load Output high voltage I = –0.2 mA Load PA7–PA0, PB7–PB0, PC6–PC0, TCMP (see Figure 13- –0.4 mA Load PD4–PD1 (see Figure 13- –1.5 mA Load PC7 Output low voltage (see ...

  • Page 177

    ... Freescale Semiconductor, Inc. MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, 5.0 4.0 3.0 2.0 1.0 0.8 SEE NOTE 2 0 0.2 0.4 V – Notes 5.0 V, devices are specified and tested for (V DD 800 –0.8 mA 3.3 V, devices are specified and tested for (V ...

  • Page 178

    ... Freescale Semiconductor, Inc. Electrical Specifications Figure 13-2. Typical Voltage Compared to Current (Continued) Technical Data 178 6.0 5.0 4.0 3.0 2.0 1.6 1.0 0 0.1 Notes 5.0 V, devices are specified and tested for DD V 400 1.6 mA 3.3 V, devices are specified and tested for ...

  • Page 179

    ... Freescale Semiconductor, Inc. MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, 3.3-Volt DC Electrical Characteristics 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.5 1.0 INTERNAL FREQUENCY 1 t CYC (a) Wait Mode 5.5 5.0 4.5 4.0 3.5 3.0 2 ...

  • Page 180

    ... Freescale Semiconductor, Inc. Electrical Specifications Technical Data 180 3 – 3.3 V 10% DD 2.5 mA 2.0 mA 1.5 mA 1.0 mA 500 250 kHz INTERNAL CLOCK FREQUENCY (XTAL (a) Maximum Current Drain versus Frequency @ 3 – 5.0 V 10% DD 6.0 mA 5.0 mA 4.0 mA 3.0 mA 2 500 kHz INTERNAL CLOCK FREQUENCY (XTAL (b) Maximum Current Drain versus Frequency @ 5 V Figure 13-4 ...

  • Page 181

    ... Freescale Semiconductor, Inc. 13.9 5.0-Volt Control Timing Characteristic Frequency of operation Crystal option External clock option Internal operating frequency Crystal (f 2) OSC External clock (f 2) OSC Cycle time (see Figure 13-7) Crystal oscillator startup time (see Stop recovery startup time (crystal oscillator) ...

  • Page 182

    ... Freescale Semiconductor, Inc. Electrical Specifications 13.10 3.3-Volt Control Timing Characteristic Frequency of operation Crystal option External clock option Internal operating frequency Crystal (f 2) OSC External clock (f 2) OSC Cycle time (see Figure 13-7) Crystal oscillator startup time (see Stop recovery startup time (crystal oscillator) ...

  • Page 183

    ... Freescale Semiconductor, Inc. (1) OSC1 t RL RESET IRQ (2) t ILIH (3) IRQ INTERNAL CLOCK INTERNAL ADDRESS BUS Notes: 1. Represents the internal gating of the OSC1 pin 2. IRQ pin edge-sensitive option 3. IRQ pin level and edge-sensitive option 4. RESET vector address shown for timing example Figure 13-6. Stop Recovery Timing Diagram MC68HC705C8A — ...

  • Page 184

    ... Freescale Semiconductor, Inc. Electrical Specifications Technical Data 184 Electrical Specifications For More Information On This Product, Go to: www.freescale.com MC68HC705C8A — Rev. 3 MOTOROLA ...

  • Page 185

    ... Freescale Semiconductor, Inc. 13.11 5.0-Volt Serial Peripheral Interface (SPI) Timing (1) Number Characteristic Operating frequency Master Slave Cycle time Master 1 Slave Enable lead time Master 2 Slave Enable lag time Master 3 Slave Clock (SCK) high time Master 4 Slave Clock (SCK) low time Master ...

  • Page 186

    ... Freescale Semiconductor, Inc. Electrical Specifications (1) Number Characteristic Data hold time (outputs) 11 Master (after capture edge) Slave (after enable edge) (7) Rise time 12 SPI outputs (SCK, MOSI, MISO) SPI inputs (SCK, MOSI, MISO, SS) (8) Fall time 13 SPI outputs (SCK, MOSI, MISO) SPI inputs (SCK, MOSI, MISO, SS) 1 ...

  • Page 187

    ... Freescale Semiconductor, Inc. 13.12 3.3-Volt Serial Peripheral Interface (SPI) Timing (1) Number Characteristic Operating frequency Master Slave Cycle time Master 1 Slave Enable lead time Master 2 Slave Enable lag time Master 3 Slave Clock (SCK) high time Master 4 Slave Clock (SCK) low time Master ...

  • Page 188

    ... Freescale Semiconductor, Inc. Electrical Specifications (1) Number Characteristic Data hold time (outputs) 11 Master (after capture edge) Slave (after enable edge) (7) Rise time 12 SPI outputs (SCK, MOSI, MISO) SPI inputs (SCK, MOSI, MISO, SS) (8) Fall time 13 SPI outputs (SCK, MOSI, MISO) SPI inputs (SCK, MOSI, MISO, SS) 1 ...

  • Page 189

    ... Freescale Semiconductor, Inc pin of master held high. INPUT SCK (CPOL = 0) NOTE OUTPUT SCK (CPOL = 1) NOTE OUTPUT MISO INPUT 10 MOSI OUTPUT 13 Note: This first clock edge is generated internally, but is not seen at the SCK pin pin of master held high. INPUT SCK (CPOL = 0) OUTPUT ...

  • Page 190

    ... Freescale Semiconductor, Inc. Electrical Specifications SS INPUT SCK (CPOL = 0) (INPUT 2 SCK (CPOL = 1) INPUT 8 MISO SLAVE INPUT 6 MOSI MSB IN OUTPUT Note: Not defined, but normally MSB of character just received SS INPUT SCK (CPOL = 0) INPUT 2 SCK (CPOL = 1) INPUT 8 MISO NOTE OUTPUT MOSI INPUT Note: Not defined, but normally LSB of character previously transmitted ...

  • Page 191

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC705C8A 14.1 Contents 14.2 14.3 14.4 14.5 14.6 14.7 14.8 14.2 Introduction Package dimensions available at the time of this publication for the MC68HC705C8A are provided in this section. The packages are: • • • • • • ...

  • Page 192

    ... Freescale Semiconductor, Inc. Mechanical Specifications 14.3 40-Pin Plastic Dual In-Line Package (PDIP Figure 14-1. MC68HC705C8AP Package Dimensions (Case #711) Technical Data 192 SEATING PLANE Mechanical Specifications For More Information On This Product, Go to: www.freescale.com MILLIMETERS INCHES DIM MIN MAX MIN A 51.69 52.45 2 ...

  • Page 193

    ... Freescale Semiconductor, Inc. 14.4 40-Pin Ceramic Dual In-Line Package (Cerdip SEATING PLANE G F Figure 14-2. MC68HC705C8AS Package Dimensions (Case #734A) MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, 40-Pin Ceramic Dual In-Line Package (Cerdip DATUM PLANE 0.25(0.010 Mechanical Specifications Go to: www.freescale.com ...

  • Page 194

    ... Freescale Semiconductor, Inc. Mechanical Specifications 14.5 44-Lead Plastic-Leaded Chip Carrier (PLCC) -N- - 0.010 (0.25) T L-M NOTES: 1. DATUMS -L-, -M-, AND -N- ARE DETERMINED WHERE TOP OF LEAD SHOLDERS EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSION R AND U DO NOT INCLUDE MOLD FLASH ...

  • Page 195

    ... Freescale Semiconductor, Inc. 14.6 44-Lead Ceramic-Leaded Chip Carrier (CLCC) - 0.25 (0.010 DETAIL S Figure 14-4. MC68HC705C8AFS Package Dimensions (Case #777B) MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, 44-Lead Ceramic-Leaded Chip Carrier (CLCC) 0.18 (0.007 BRK DETAIL D 0.20 (0.008 0.18 (0.007) ...

  • Page 196

    ... Freescale Semiconductor, Inc. Mechanical Specifications 14.7 44-Pin Quad Flat Pack (QFP - -D- 0.20 (0.008) 0.05 (0.002) A-B 0.20 (0.008 -C- H SEATING PLANE G DATUM -H- PLANE W DETAIL C Figure 14-5. MC68HC705C8AFB Package Dimensions (Case #824A) Technical Data 196 -B- DETAIL A A DETAIL C DATUM -H- PLANE 0.01 (0.004) ...

  • Page 197

    ... Freescale Semiconductor, Inc. 14.8 42-Pin Shrink Dual In-Line Package (SDIP) - -T- SEATING PLANE 0.25 (0.010 Figure 14-6. MC68HC705C8AB Package Dimensions (Case #858) MC68HC705C8A — Rev. 3 MOTOROLA For More Information On This Product, 42-Pin Shrink Dual In-Line Package (SDIP 0.25 (0.010 Mechanical Specifications Go to: www.freescale.com ...

  • Page 198

    ... Freescale Semiconductor, Inc. Mechanical Specifications Technical Data 198 Mechanical Specifications For More Information On This Product, Go to: www.freescale.com MC68HC705C8A — Rev. 3 MOTOROLA ...

  • Page 199

    ... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 lists the MC order numbers. Temperature Range – +85 C – +85 C – +85 C – +85 C – +85 C – +85 C Ordering Information Go to: www.freescale.com Order Number (1) (2) MC68HC705C8AC P (3) MC68HC705C8ACFN (4) MC68HC705C8ACFS (5) MC68HC705C8ACS (6) MC68HC705C8ACFB (7) MC68HC705C8ACB Technical Data 199 ...

  • Page 200

    ... Freescale Semiconductor, Inc. Ordering Information Technical Data 200 Ordering Information For More Information On This Product, Go to: www.freescale.com MC68HC705C8A — Rev. 3 MOTOROLA ...